| [6f8a426] | 1 | #
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| [df4ed85] | 2 | # Copyright (c) 2006 Martin Decky
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| [6f8a426] | 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | #include <arch/asm/regname.h>
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| 30 | #include <arch/context_offset.h>
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| 31 |
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| 32 | .text
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| 33 |
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| 34 | .global fpu_context_save
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| 35 | .global fpu_context_restore
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| [8b1439e] | 36 | .global fpu_init
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| 37 | .global fpu_enable
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| 38 | .global fpu_disable
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| [6f8a426] | 39 |
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| 40 | .macro FPU_CONTEXT_STORE r
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| 41 | stfd fr14, OFFSET_FR14(\r)
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| 42 | stfd fr15, OFFSET_FR15(\r)
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| 43 | stfd fr16, OFFSET_FR16(\r)
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| 44 | stfd fr17, OFFSET_FR17(\r)
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| 45 | stfd fr18, OFFSET_FR18(\r)
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| 46 | stfd fr19, OFFSET_FR19(\r)
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| 47 | stfd fr20, OFFSET_FR20(\r)
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| 48 | stfd fr21, OFFSET_FR21(\r)
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| 49 | stfd fr22, OFFSET_FR22(\r)
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| 50 | stfd fr23, OFFSET_FR23(\r)
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| 51 | stfd fr24, OFFSET_FR24(\r)
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| 52 | stfd fr25, OFFSET_FR25(\r)
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| 53 | stfd fr26, OFFSET_FR26(\r)
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| 54 | stfd fr27, OFFSET_FR27(\r)
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| 55 | stfd fr28, OFFSET_FR28(\r)
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| 56 | stfd fr29, OFFSET_FR29(\r)
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| 57 | stfd fr30, OFFSET_FR30(\r)
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| 58 | stfd fr31, OFFSET_FR31(\r)
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| 59 | .endm
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| 60 |
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| 61 | .macro FPU_CONTEXT_LOAD r
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| 62 | lfd fr14, OFFSET_FR14(\r)
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| 63 | lfd fr15, OFFSET_FR15(\r)
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| 64 | lfd fr16, OFFSET_FR16(\r)
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| 65 | lfd fr17, OFFSET_FR17(\r)
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| 66 | lfd fr18, OFFSET_FR18(\r)
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| 67 | lfd fr19, OFFSET_FR19(\r)
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| 68 | lfd fr20, OFFSET_FR20(\r)
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| 69 | lfd fr21, OFFSET_FR21(\r)
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| 70 | lfd fr22, OFFSET_FR22(\r)
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| 71 | lfd fr23, OFFSET_FR23(\r)
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| 72 | lfd fr24, OFFSET_FR24(\r)
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| 73 | lfd fr25, OFFSET_FR25(\r)
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| 74 | lfd fr26, OFFSET_FR26(\r)
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| 75 | lfd fr27, OFFSET_FR27(\r)
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| 76 | lfd fr28, OFFSET_FR28(\r)
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| 77 | lfd fr29, OFFSET_FR29(\r)
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| 78 | lfd fr30, OFFSET_FR30(\r)
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| 79 | lfd fr31, OFFSET_FR31(\r)
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| 80 | .endm
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| 81 |
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| 82 | fpu_context_save:
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| [8965838e] | 83 | // FPU_CONTEXT_STORE r3
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| 84 | //
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| 85 | // mffs fr0
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| 86 | // stfd fr0, OFFSET_FPSCR(r3)
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| [6f8a426] | 87 |
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| 88 | blr
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| 89 |
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| 90 | fpu_context_restore:
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| [8965838e] | 91 | // FPU_CONTEXT_LOAD r3
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| 92 | //
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| 93 | // lfd fr0, OFFSET_FPSCR(r3)
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| 94 | // mtfsf 7, fr0
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| [6f8a426] | 95 |
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| 96 | blr
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| [8b1439e] | 97 |
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| 98 | fpu_init:
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| 99 | blr
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| 100 |
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| 101 | fpu_enable:
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| 102 | blr
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| 103 |
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| 104 | fpu_disable:
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| 105 | blr
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