source: mainline/kernel/arch/ppc32/src/fpu_context.S

Last change on this file was a35b458, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 7 years ago

style: Remove trailing whitespace on _all_ lines, including empty ones, for particular file types.

Command used: tools/srepl '\s\+$' '' -- *.c *.h *.py *.sh *.s *.S *.ag

Currently, whitespace on empty lines is very inconsistent.
There are two basic choices: Either remove the whitespace, or keep empty lines
indented to the level of surrounding code. The former is AFAICT more common,
and also much easier to do automatically.

Alternatively, we could write script for automatic indentation, and use that
instead. However, if such a script exists, it's possible to use the indented
style locally, by having the editor apply relevant conversions on load/save,
without affecting remote repository. IMO, it makes more sense to adopt
the simpler rule.
  • Property mode set to 100644
File size: 4.7 KB
RevLine 
[6f8a426]1#
[df4ed85]2# Copyright (c) 2006 Martin Decky
[6f8a426]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[b66cc97]29#include <abi/asmtool.h>
[6f8a426]30#include <arch/asm/regname.h>
[a595f5a]31#include <arch/fpu_context_struct.h>
[df7f5cea]32#include <arch/msr.h>
[6f8a426]33
[b8230b9]34.text
[6f8a426]35
36.macro FPU_CONTEXT_STORE r
[a595f5a]37 stfd fr0, FPU_CONTEXT_OFFSET_FR0(\r)
38 stfd fr1, FPU_CONTEXT_OFFSET_FR1(\r)
39 stfd fr2, FPU_CONTEXT_OFFSET_FR2(\r)
40 stfd fr3, FPU_CONTEXT_OFFSET_FR3(\r)
41 stfd fr4, FPU_CONTEXT_OFFSET_FR4(\r)
42 stfd fr5, FPU_CONTEXT_OFFSET_FR5(\r)
43 stfd fr6, FPU_CONTEXT_OFFSET_FR6(\r)
44 stfd fr7, FPU_CONTEXT_OFFSET_FR7(\r)
45 stfd fr8, FPU_CONTEXT_OFFSET_FR8(\r)
46 stfd fr9, FPU_CONTEXT_OFFSET_FR9(\r)
47 stfd fr10, FPU_CONTEXT_OFFSET_FR10(\r)
48 stfd fr11, FPU_CONTEXT_OFFSET_FR11(\r)
49 stfd fr12, FPU_CONTEXT_OFFSET_FR12(\r)
50 stfd fr13, FPU_CONTEXT_OFFSET_FR13(\r)
51 stfd fr14, FPU_CONTEXT_OFFSET_FR14(\r)
52 stfd fr15, FPU_CONTEXT_OFFSET_FR15(\r)
53 stfd fr16, FPU_CONTEXT_OFFSET_FR16(\r)
54 stfd fr17, FPU_CONTEXT_OFFSET_FR17(\r)
55 stfd fr18, FPU_CONTEXT_OFFSET_FR18(\r)
56 stfd fr19, FPU_CONTEXT_OFFSET_FR19(\r)
57 stfd fr20, FPU_CONTEXT_OFFSET_FR20(\r)
58 stfd fr21, FPU_CONTEXT_OFFSET_FR21(\r)
59 stfd fr22, FPU_CONTEXT_OFFSET_FR22(\r)
60 stfd fr23, FPU_CONTEXT_OFFSET_FR23(\r)
61 stfd fr24, FPU_CONTEXT_OFFSET_FR24(\r)
62 stfd fr25, FPU_CONTEXT_OFFSET_FR25(\r)
63 stfd fr26, FPU_CONTEXT_OFFSET_FR26(\r)
64 stfd fr27, FPU_CONTEXT_OFFSET_FR27(\r)
65 stfd fr28, FPU_CONTEXT_OFFSET_FR28(\r)
66 stfd fr29, FPU_CONTEXT_OFFSET_FR29(\r)
67 stfd fr30, FPU_CONTEXT_OFFSET_FR30(\r)
68 stfd fr31, FPU_CONTEXT_OFFSET_FR31(\r)
[6f8a426]69.endm
70
71.macro FPU_CONTEXT_LOAD r
[a595f5a]72 lfd fr0, FPU_CONTEXT_OFFSET_FR0(\r)
73 lfd fr1, FPU_CONTEXT_OFFSET_FR1(\r)
74 lfd fr2, FPU_CONTEXT_OFFSET_FR2(\r)
75 lfd fr3, FPU_CONTEXT_OFFSET_FR3(\r)
76 lfd fr4, FPU_CONTEXT_OFFSET_FR4(\r)
77 lfd fr5, FPU_CONTEXT_OFFSET_FR5(\r)
78 lfd fr6, FPU_CONTEXT_OFFSET_FR6(\r)
79 lfd fr7, FPU_CONTEXT_OFFSET_FR7(\r)
80 lfd fr8, FPU_CONTEXT_OFFSET_FR8(\r)
81 lfd fr9, FPU_CONTEXT_OFFSET_FR9(\r)
82 lfd fr10, FPU_CONTEXT_OFFSET_FR10(\r)
83 lfd fr11, FPU_CONTEXT_OFFSET_FR11(\r)
84 lfd fr12, FPU_CONTEXT_OFFSET_FR12(\r)
85 lfd fr13, FPU_CONTEXT_OFFSET_FR13(\r)
86 lfd fr14, FPU_CONTEXT_OFFSET_FR14(\r)
87 lfd fr15, FPU_CONTEXT_OFFSET_FR15(\r)
88 lfd fr16, FPU_CONTEXT_OFFSET_FR16(\r)
89 lfd fr17, FPU_CONTEXT_OFFSET_FR17(\r)
90 lfd fr18, FPU_CONTEXT_OFFSET_FR18(\r)
91 lfd fr19, FPU_CONTEXT_OFFSET_FR19(\r)
92 lfd fr20, FPU_CONTEXT_OFFSET_FR20(\r)
93 lfd fr21, FPU_CONTEXT_OFFSET_FR21(\r)
94 lfd fr22, FPU_CONTEXT_OFFSET_FR22(\r)
95 lfd fr23, FPU_CONTEXT_OFFSET_FR23(\r)
96 lfd fr24, FPU_CONTEXT_OFFSET_FR24(\r)
97 lfd fr25, FPU_CONTEXT_OFFSET_FR25(\r)
98 lfd fr26, FPU_CONTEXT_OFFSET_FR26(\r)
99 lfd fr27, FPU_CONTEXT_OFFSET_FR27(\r)
100 lfd fr28, FPU_CONTEXT_OFFSET_FR28(\r)
101 lfd fr29, FPU_CONTEXT_OFFSET_FR29(\r)
102 lfd fr30, FPU_CONTEXT_OFFSET_FR30(\r)
103 lfd fr31, FPU_CONTEXT_OFFSET_FR31(\r)
[6f8a426]104.endm
105
[b66cc97]106FUNCTION_BEGIN(fpu_context_save)
[df7f5cea]107 FPU_CONTEXT_STORE r3
[a35b458]108
[df7f5cea]109 mffs fr0
[a595f5a]110 stfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3)
[a35b458]111
[6f8a426]112 blr
[b66cc97]113FUNCTION_END(fpu_context_save)
[b8230b9]114
[b66cc97]115FUNCTION_BEGIN(fpu_context_restore)
[a595f5a]116 lfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3)
[5a42886]117 mtfsf 0xff, fr0
[a35b458]118
[df7f5cea]119 FPU_CONTEXT_LOAD r3
[a35b458]120
[6f8a426]121 blr
[b66cc97]122FUNCTION_END(fpu_context_restore)
[8b1439e]123
[b66cc97]124FUNCTION_BEGIN(fpu_init)
[df7f5cea]125 mfmsr r0
126 ori r0, r0, MSR_FP
[a35b458]127
[df7f5cea]128 # Disable FPU exceptions
129 li r3, MSR_FE0 | MSR_FE1
130 andc r0, r0, r3
[a35b458]131
[df7f5cea]132 mtmsr r0
[5a42886]133 isync
[a35b458]134
[8b1439e]135 blr
[b66cc97]136FUNCTION_END(fpu_init)
[8b1439e]137
[b66cc97]138FUNCTION_BEGIN(fpu_enable)
[df7f5cea]139 mfmsr r0
140 ori r0, r0, MSR_FP
141 mtmsr r0
[5a42886]142 isync
[8b1439e]143 blr
[b66cc97]144FUNCTION_END(fpu_enable)
[8b1439e]145
[b66cc97]146FUNCTION_BEGIN(fpu_disable)
[df7f5cea]147 mfmsr r0
148 li r3, MSR_FP
149 andc r0, r0, r3
150 mtmsr r0
[5a42886]151 isync
[8b1439e]152 blr
[b66cc97]153FUNCTION_END(fpu_disable)
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