source: mainline/kernel/arch/ppc32/src/asm.S@ 39aa8ce

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 39aa8ce was c0699467, checked in by Martin Decky <martin@…>, 14 years ago

do not provide general access to kernel headers from uspace, only allow specific headers to be accessed or shared
externalize headers which serve as kernel/uspace API/ABI into a special tree
  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 * Copyright (c) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/asm/regname.h>
30#include <arch/msr.h>
31
32.text
33
34.global userspace_asm
35.global iret
36.global iret_syscall
37.global memcpy_from_uspace
38.global memcpy_to_uspace
39.global memcpy_from_uspace_failover_address
40.global memcpy_to_uspace_failover_address
41.global early_putchar
42
43userspace_asm:
44
45 /*
46 * r3 = uspace_uarg
47 * r4 = stack
48 * r5 = entry
49 */
50
51 /* Disable interrupts */
52
53 mfmsr r31
54 rlwinm r31, r31, 0, 17, 15
55 mtmsr r31
56
57 /* Set entry point */
58
59 mtsrr0 r5
60
61 /* Set problem state, enable interrupts */
62
63 ori r31, r31, MSR_PR
64 ori r31, r31, MSR_EE
65 mtsrr1 r31
66
67 /* Set stack */
68
69 mr sp, r4
70
71 /* %r6 is defined to hold pcb_ptr - set it to 0 */
72
73 xor r6, r6, r6
74
75 /* Jump to userspace */
76
77 rfi
78
79iret:
80
81 /* Disable interrupts */
82
83 mfmsr r31
84 rlwinm r31, r31, 0, 17, 15
85 mtmsr r31
86
87 lwz r0, 8(sp)
88 lwz r2, 12(sp)
89 lwz r3, 16(sp)
90 lwz r4, 20(sp)
91 lwz r5, 24(sp)
92 lwz r6, 28(sp)
93 lwz r7, 32(sp)
94 lwz r8, 36(sp)
95 lwz r9, 40(sp)
96 lwz r10, 44(sp)
97 lwz r11, 48(sp)
98 lwz r13, 52(sp)
99 lwz r14, 56(sp)
100 lwz r15, 60(sp)
101 lwz r16, 64(sp)
102 lwz r17, 68(sp)
103 lwz r18, 72(sp)
104 lwz r19, 76(sp)
105 lwz r20, 80(sp)
106 lwz r21, 84(sp)
107 lwz r22, 88(sp)
108 lwz r23, 92(sp)
109 lwz r24, 96(sp)
110 lwz r25, 100(sp)
111 lwz r26, 104(sp)
112 lwz r27, 108(sp)
113 lwz r28, 112(sp)
114 lwz r29, 116(sp)
115 lwz r30, 120(sp)
116 lwz r31, 124(sp)
117
118 lwz r12, 128(sp)
119 mtcr r12
120
121 lwz r12, 132(sp)
122 mtsrr0 r12
123
124 lwz r12, 136(sp)
125 mtsrr1 r12
126
127 lwz r12, 140(sp)
128 mtlr r12
129
130 lwz r12, 144(sp)
131 mtctr r12
132
133 lwz r12, 148(sp)
134 mtxer r12
135
136 lwz r12, 156(sp)
137 lwz sp, 160(sp)
138
139 rfi
140
141iret_syscall:
142
143 /* Reset decrementer */
144
145 li r31, 1000
146 mtdec r31
147
148 /* Disable interrupts */
149
150 mfmsr r31
151 rlwinm r31, r31, 0, 17, 15
152 mtmsr r31
153
154 lwz r0, 8(sp)
155 lwz r2, 12(sp)
156 lwz r4, 20(sp)
157 lwz r5, 24(sp)
158 lwz r6, 28(sp)
159 lwz r7, 32(sp)
160 lwz r8, 36(sp)
161 lwz r9, 40(sp)
162 lwz r10, 44(sp)
163 lwz r11, 48(sp)
164 lwz r13, 52(sp)
165 lwz r14, 56(sp)
166 lwz r15, 60(sp)
167 lwz r16, 64(sp)
168 lwz r17, 68(sp)
169 lwz r18, 72(sp)
170 lwz r19, 76(sp)
171 lwz r20, 80(sp)
172 lwz r21, 84(sp)
173 lwz r22, 88(sp)
174 lwz r23, 92(sp)
175 lwz r24, 96(sp)
176 lwz r25, 100(sp)
177 lwz r26, 104(sp)
178 lwz r27, 108(sp)
179 lwz r28, 112(sp)
180 lwz r29, 116(sp)
181 lwz r30, 120(sp)
182 lwz r31, 124(sp)
183
184 lwz r12, 128(sp)
185 mtcr r12
186
187 lwz r12, 132(sp)
188 mtsrr0 r12
189
190 lwz r12, 136(sp)
191 mtsrr1 r12
192
193 lwz r12, 140(sp)
194 mtlr r12
195
196 lwz r12, 144(sp)
197 mtctr r12
198
199 lwz r12, 148(sp)
200 mtxer r12
201
202 lwz r12, 156(sp)
203 lwz sp, 160(sp)
204
205 rfi
206
207memcpy_from_uspace:
208memcpy_to_uspace:
209
210 srwi. r7, r5, 3
211 addi r6, r3, -4
212 addi r4, r4, -4
213 beq 2f
214
215 andi. r0, r6, 3
216 mtctr r7
217 bne 5f
218
219 1:
220
221 lwz r7, 4(r4)
222 lwzu r8, 8(r4)
223 stw r7, 4(r6)
224 stwu r8, 8(r6)
225 bdnz 1b
226
227 andi. r5, r5, 7
228
229 2:
230
231 cmplwi 0, r5, 4
232 blt 3f
233
234 lwzu r0, 4(r4)
235 addi r5, r5, -4
236 stwu r0, 4(r6)
237
238 3:
239
240 cmpwi 0, r5, 0
241 beqlr
242 mtctr r5
243 addi r4, r4, 3
244 addi r6, r6, 3
245
246 4:
247
248 lbzu r0, 1(r4)
249 stbu r0, 1(r6)
250 bdnz 4b
251 blr
252
253 5:
254
255 subfic r0, r0, 4
256 mtctr r0
257
258 6:
259
260 lbz r7, 4(r4)
261 addi r4, r4, 1
262 stb r7, 4(r6)
263 addi r6, r6, 1
264 bdnz 6b
265 subf r5, r0, r5
266 rlwinm. r7, r5, 32-3, 3, 31
267 beq 2b
268 mtctr r7
269 b 1b
270
271memcpy_from_uspace_failover_address:
272memcpy_to_uspace_failover_address:
273 /* Return zero, failure */
274 xor r3, r3, r3
275 blr
276
277early_putchar:
278 blr
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