source: mainline/kernel/arch/ppc32/src/asm.S@ 15d0046

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 15d0046 was 52c0b8c, checked in by Jakub Jermar <jakub@…>, 11 years ago

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1/*
2 * Copyright (c) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/asm/regname.h>
30#include <arch/msr.h>
31#include <arch/istate_struct.h>
32
33.text
34
35.global userspace_asm
36.global iret
37.global iret_syscall
38.global memcpy_from_uspace
39.global memcpy_to_uspace
40.global memcpy_from_uspace_failover_address
41.global memcpy_to_uspace_failover_address
42.global early_putchar
43
44userspace_asm:
45
46 /*
47 * r3 = uspace_uarg
48 * r4 = stack
49 * r5 = entry
50 */
51
52 /* Disable interrupts */
53
54 mfmsr r31
55 rlwinm r31, r31, 0, 17, 15
56 mtmsr r31
57
58 /* Set entry point */
59
60 mtsrr0 r5
61
62 /* Set privileged state, enable interrupts */
63
64 ori r31, r31, MSR_PR
65 ori r31, r31, MSR_EE
66 mtsrr1 r31
67
68 /* Set stack */
69
70 mr sp, r4
71
72 /* %r6 is defined to hold pcb_ptr - set it to 0 */
73
74 xor r6, r6, r6
75
76 /* Jump to userspace */
77
78 rfi
79
80iret:
81
82 /* Disable interrupts */
83
84 mfmsr r31
85 rlwinm r31, r31, 0, 17, 15
86 mtmsr r31
87
88 lwz r0, ISTATE_OFFSET_R0(sp)
89 lwz r2, ISTATE_OFFSET_R2(sp)
90 lwz r3, ISTATE_OFFSET_R3(sp)
91 lwz r4, ISTATE_OFFSET_R4(sp)
92 lwz r5, ISTATE_OFFSET_R5(sp)
93 lwz r6, ISTATE_OFFSET_R6(sp)
94 lwz r7, ISTATE_OFFSET_R7(sp)
95 lwz r8, ISTATE_OFFSET_R8(sp)
96 lwz r9, ISTATE_OFFSET_R9(sp)
97 lwz r10, ISTATE_OFFSET_R10(sp)
98 lwz r11, ISTATE_OFFSET_R11(sp)
99 lwz r13, ISTATE_OFFSET_R13(sp)
100 lwz r14, ISTATE_OFFSET_R14(sp)
101 lwz r15, ISTATE_OFFSET_R15(sp)
102 lwz r16, ISTATE_OFFSET_R16(sp)
103 lwz r17, ISTATE_OFFSET_R17(sp)
104 lwz r18, ISTATE_OFFSET_R18(sp)
105 lwz r19, ISTATE_OFFSET_R19(sp)
106 lwz r20, ISTATE_OFFSET_R20(sp)
107 lwz r21, ISTATE_OFFSET_R21(sp)
108 lwz r22, ISTATE_OFFSET_R22(sp)
109 lwz r23, ISTATE_OFFSET_R23(sp)
110 lwz r24, ISTATE_OFFSET_R24(sp)
111 lwz r25, ISTATE_OFFSET_R25(sp)
112 lwz r26, ISTATE_OFFSET_R26(sp)
113 lwz r27, ISTATE_OFFSET_R27(sp)
114 lwz r28, ISTATE_OFFSET_R28(sp)
115 lwz r29, ISTATE_OFFSET_R29(sp)
116 lwz r30, ISTATE_OFFSET_R30(sp)
117 lwz r31, ISTATE_OFFSET_R31(sp)
118
119 lwz r12, ISTATE_OFFSET_CR(sp)
120 mtcr r12
121
122 lwz r12, ISTATE_OFFSET_PC(sp)
123 mtsrr0 r12
124
125 lwz r12, ISTATE_OFFSET_SRR1(sp)
126 mtsrr1 r12
127
128 lwz r12, ISTATE_OFFSET_LR(sp)
129 mtlr r12
130
131 lwz r12, ISTATE_OFFSET_CTR(sp)
132 mtctr r12
133
134 lwz r12, ISTATE_OFFSET_XER(sp)
135 mtxer r12
136
137 lwz r12, ISTATE_OFFSET_R12(sp)
138 lwz sp, ISTATE_OFFSET_SP(sp)
139
140 rfi
141
142iret_syscall:
143
144 /* Reset decrementer */
145
146 li r31, 1000
147 mtdec r31
148
149 /* Disable interrupts */
150
151 mfmsr r31
152 rlwinm r31, r31, 0, 17, 15
153 mtmsr r31
154
155 lwz r0, ISTATE_OFFSET_R0(sp)
156 lwz r2, ISTATE_OFFSET_R2(sp)
157 lwz r4, ISTATE_OFFSET_R4(sp)
158 lwz r5, ISTATE_OFFSET_R5(sp)
159 lwz r6, ISTATE_OFFSET_R6(sp)
160 lwz r7, ISTATE_OFFSET_R7(sp)
161 lwz r8, ISTATE_OFFSET_R8(sp)
162 lwz r9, ISTATE_OFFSET_R9(sp)
163 lwz r10, ISTATE_OFFSET_R10(sp)
164 lwz r11, ISTATE_OFFSET_R11(sp)
165 lwz r13, ISTATE_OFFSET_R13(sp)
166 lwz r14, ISTATE_OFFSET_R14(sp)
167 lwz r15, ISTATE_OFFSET_R15(sp)
168 lwz r16, ISTATE_OFFSET_R16(sp)
169 lwz r17, ISTATE_OFFSET_R17(sp)
170 lwz r18, ISTATE_OFFSET_R18(sp)
171 lwz r19, ISTATE_OFFSET_R19(sp)
172 lwz r20, ISTATE_OFFSET_R20(sp)
173 lwz r21, ISTATE_OFFSET_R21(sp)
174 lwz r22, ISTATE_OFFSET_R22(sp)
175 lwz r23, ISTATE_OFFSET_R23(sp)
176 lwz r24, ISTATE_OFFSET_R24(sp)
177 lwz r25, ISTATE_OFFSET_R25(sp)
178 lwz r26, ISTATE_OFFSET_R26(sp)
179 lwz r27, ISTATE_OFFSET_R27(sp)
180 lwz r28, ISTATE_OFFSET_R28(sp)
181 lwz r29, ISTATE_OFFSET_R29(sp)
182 lwz r30, ISTATE_OFFSET_R30(sp)
183 lwz r31, ISTATE_OFFSET_R31(sp)
184
185 lwz r12, ISTATE_OFFSET_CR(sp)
186 mtcr r12
187
188 lwz r12, ISTATE_OFFSET_PC(sp)
189 mtsrr0 r12
190
191 lwz r12, ISTATE_OFFSET_SRR1(sp)
192 mtsrr1 r12
193
194 lwz r12, ISTATE_OFFSET_LR(sp)
195 mtlr r12
196
197 lwz r12, ISTATE_OFFSET_CTR(sp)
198 mtctr r12
199
200 lwz r12, ISTATE_OFFSET_XER(sp)
201 mtxer r12
202
203 lwz r12, ISTATE_OFFSET_R12(sp)
204 lwz sp, ISTATE_OFFSET_SP(sp)
205
206 rfi
207
208memcpy_from_uspace:
209memcpy_to_uspace:
210
211 srwi. r7, r5, 3
212 addi r6, r3, -4
213 addi r4, r4, -4
214 beq 2f
215
216 andi. r0, r6, 3
217 mtctr r7
218 bne 5f
219
220 1:
221
222 lwz r7, 4(r4)
223 lwzu r8, 8(r4)
224 stw r7, 4(r6)
225 stwu r8, 8(r6)
226 bdnz 1b
227
228 andi. r5, r5, 7
229
230 2:
231
232 cmplwi 0, r5, 4
233 blt 3f
234
235 lwzu r0, 4(r4)
236 addi r5, r5, -4
237 stwu r0, 4(r6)
238
239 3:
240
241 cmpwi 0, r5, 0
242 beqlr
243 mtctr r5
244 addi r4, r4, 3
245 addi r6, r6, 3
246
247 4:
248
249 lbzu r0, 1(r4)
250 stbu r0, 1(r6)
251 bdnz 4b
252 blr
253
254 5:
255
256 subfic r0, r0, 4
257 mtctr r0
258
259 6:
260
261 lbz r7, 4(r4)
262 addi r4, r4, 1
263 stb r7, 4(r6)
264 addi r6, r6, 1
265 bdnz 6b
266 subf r5, r0, r5
267 rlwinm. r7, r5, 32-3, 3, 31
268 beq 2b
269 mtctr r7
270 b 1b
271
272memcpy_from_uspace_failover_address:
273memcpy_to_uspace_failover_address:
274 /* Return zero, failure */
275 xor r3, r3, r3
276 blr
277
278early_putchar:
279 blr
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