| [efa9b73] | 1 | #
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| [df4ed85] | 2 | # Copyright (c) 2005 Martin Decky
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| [efa9b73] | 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| [37c8975] | 29 | #include <arch/asm/regname.h>
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| [10caad0] | 30 |
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| [efa9b73] | 31 | .text
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| 32 |
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| [e692a27] | 33 | .global userspace_asm
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| [91d5ad6] | 34 | .global iret
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| [e34a141] | 35 | .global iret_syscall
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| [393f631] | 36 | .global memsetb
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| [b60c582] | 37 | .global memsetw
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| [393f631] | 38 | .global memcpy
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| [e3c762cd] | 39 | .global memcpy_from_uspace
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| 40 | .global memcpy_to_uspace
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| 41 | .global memcpy_from_uspace_failover_address
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| 42 | .global memcpy_to_uspace_failover_address
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| [dfbc229] | 43 |
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| [e692a27] | 44 | userspace_asm:
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| 45 |
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| 46 | # r3 = uspace_uarg
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| 47 | # r4 = stack
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| [762a824] | 48 | # r5 = entry
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| 49 |
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| 50 | # disable interrupts
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| [e692a27] | 51 |
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| 52 | mfmsr r31
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| 53 | rlwinm r31, r31, 0, 17, 15
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| 54 | mtmsr r31
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| 55 |
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| 56 | # set entry point
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| 57 |
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| 58 | mtsrr0 r5
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| 59 |
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| 60 | # set problem state, enable interrupts
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| 61 |
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| [762a824] | 62 | ori r31, r31, msr_pr
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| 63 | ori r31, r31, msr_ee
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| [e692a27] | 64 | mtsrr1 r31
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| 65 |
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| 66 | # set stack
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| 67 |
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| 68 | mr sp, r4
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| [c98e6ee] | 69 |
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| [c1b455e] | 70 | # %r6 is defined to hold pcb_ptr - set it to 0
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| [c98e6ee] | 71 |
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| [c1b455e] | 72 | xor r6, r6, r6
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| [e692a27] | 73 |
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| 74 | # jump to userspace
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| 75 |
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| 76 | rfi
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| 77 |
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| [91d5ad6] | 78 | iret:
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| [e34a141] | 79 |
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| 80 | # disable interrupts
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| 81 |
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| 82 | mfmsr r31
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| 83 | rlwinm r31, r31, 0, 17, 15
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| 84 | mtmsr r31
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| 85 |
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| [2e2d654] | 86 | lwz r0, 8(sp)
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| 87 | lwz r2, 12(sp)
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| 88 | lwz r3, 16(sp)
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| 89 | lwz r4, 20(sp)
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| 90 | lwz r5, 24(sp)
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| 91 | lwz r6, 28(sp)
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| 92 | lwz r7, 32(sp)
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| 93 | lwz r8, 36(sp)
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| 94 | lwz r9, 40(sp)
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| 95 | lwz r10, 44(sp)
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| 96 | lwz r11, 48(sp)
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| 97 | lwz r13, 52(sp)
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| 98 | lwz r14, 56(sp)
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| 99 | lwz r15, 60(sp)
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| 100 | lwz r16, 64(sp)
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| 101 | lwz r17, 68(sp)
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| 102 | lwz r18, 72(sp)
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| 103 | lwz r19, 76(sp)
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| 104 | lwz r20, 80(sp)
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| 105 | lwz r21, 84(sp)
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| 106 | lwz r22, 88(sp)
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| 107 | lwz r23, 92(sp)
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| 108 | lwz r24, 96(sp)
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| 109 | lwz r25, 100(sp)
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| 110 | lwz r26, 104(sp)
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| 111 | lwz r27, 108(sp)
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| 112 | lwz r28, 112(sp)
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| 113 | lwz r29, 116(sp)
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| 114 | lwz r30, 120(sp)
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| 115 | lwz r31, 124(sp)
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| 116 |
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| 117 | lwz r12, 128(sp)
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| [e34a141] | 118 | mtcr r12
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| [762a824] | 119 |
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| [2e2d654] | 120 | lwz r12, 132(sp)
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| [e34a141] | 121 | mtsrr0 r12
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| [762a824] | 122 |
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| [2e2d654] | 123 | lwz r12, 136(sp)
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| [e34a141] | 124 | mtsrr1 r12
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| [762a824] | 125 |
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| [2e2d654] | 126 | lwz r12, 140(sp)
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| [e34a141] | 127 | mtlr r12
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| [762a824] | 128 |
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| [2e2d654] | 129 | lwz r12, 144(sp)
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| [762a824] | 130 | mtctr r12
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| 131 |
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| [2e2d654] | 132 | lwz r12, 148(sp)
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| [762a824] | 133 | mtxer r12
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| [e34a141] | 134 |
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| [826c203] | 135 | lwz r12, 156(sp)
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| 136 | lwz sp, 160(sp)
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| [e34a141] | 137 |
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| 138 | rfi
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| [762a824] | 139 |
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| [e34a141] | 140 | iret_syscall:
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| [91d5ad6] | 141 |
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| [a33c990] | 142 | # reset decrementer
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| 143 |
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| 144 | li r31, 1000
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| 145 | mtdec r31
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| 146 |
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| [e34a141] | 147 | # disable interrupts
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| 148 |
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| 149 | mfmsr r31
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| 150 | rlwinm r31, r31, 0, 17, 15
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| 151 | mtmsr r31
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| 152 |
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| [2e2d654] | 153 | lwz r0, 8(sp)
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| 154 | lwz r2, 12(sp)
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| 155 | lwz r4, 20(sp)
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| 156 | lwz r5, 24(sp)
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| 157 | lwz r6, 28(sp)
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| 158 | lwz r7, 32(sp)
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| 159 | lwz r8, 36(sp)
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| 160 | lwz r9, 40(sp)
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| 161 | lwz r10, 44(sp)
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| 162 | lwz r11, 48(sp)
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| 163 | lwz r13, 52(sp)
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| 164 | lwz r14, 56(sp)
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| 165 | lwz r15, 60(sp)
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| 166 | lwz r16, 64(sp)
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| 167 | lwz r17, 68(sp)
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| 168 | lwz r18, 72(sp)
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| 169 | lwz r19, 76(sp)
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| 170 | lwz r20, 80(sp)
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| 171 | lwz r21, 84(sp)
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| 172 | lwz r22, 88(sp)
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| 173 | lwz r23, 92(sp)
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| 174 | lwz r24, 96(sp)
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| 175 | lwz r25, 100(sp)
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| 176 | lwz r26, 104(sp)
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| 177 | lwz r27, 108(sp)
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| 178 | lwz r28, 112(sp)
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| 179 | lwz r29, 116(sp)
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| 180 | lwz r30, 120(sp)
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| 181 | lwz r31, 124(sp)
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| 182 |
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| 183 | lwz r12, 128(sp)
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| [e34a141] | 184 | mtcr r12
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| 185 |
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| [2e2d654] | 186 | lwz r12, 132(sp)
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| [e34a141] | 187 | mtsrr0 r12
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| 188 |
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| [2e2d654] | 189 | lwz r12, 136(sp)
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| [e34a141] | 190 | mtsrr1 r12
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| 191 |
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| [2e2d654] | 192 | lwz r12, 140(sp)
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| [e34a141] | 193 | mtlr r12
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| 194 |
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| [2e2d654] | 195 | lwz r12, 144(sp)
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| [e34a141] | 196 | mtctr r12
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| 197 |
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| [2e2d654] | 198 | lwz r12, 148(sp)
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| [e34a141] | 199 | mtxer r12
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| 200 |
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| [826c203] | 201 | lwz r12, 156(sp)
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| 202 | lwz sp, 160(sp)
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| [e34a141] | 203 |
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| [91d5ad6] | 204 | rfi
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| [b60c582] | 205 |
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| [393f631] | 206 | memsetb:
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| [7560b606] | 207 | b _memsetb
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| [393f631] | 208 |
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| [b60c582] | 209 | memsetw:
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| 210 | b _memsetw
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| 211 |
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| [393f631] | 212 | memcpy:
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| [e3c762cd] | 213 | memcpy_from_uspace:
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| 214 | memcpy_to_uspace:
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| 215 |
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| [6f8a426] | 216 | srwi. r7, r5, 3
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| 217 | addi r6, r3, -4
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| 218 | addi r4, r4, -4
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| 219 | beq 2f
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| 220 |
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| 221 | andi. r0, r6, 3
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| 222 | mtctr r7
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| 223 | bne 5f
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| 224 |
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| 225 | 1:
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| 226 |
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| 227 | lwz r7, 4(r4)
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| 228 | lwzu r8, 8(r4)
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| 229 | stw r7, 4(r6)
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| 230 | stwu r8, 8(r6)
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| 231 | bdnz 1b
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| 232 |
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| 233 | andi. r5, r5, 7
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| 234 |
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| 235 | 2:
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| 236 |
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| 237 | cmplwi 0, r5, 4
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| 238 | blt 3f
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| 239 |
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| 240 | lwzu r0, 4(r4)
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| 241 | addi r5, r5, -4
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| 242 | stwu r0, 4(r6)
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| 243 |
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| 244 | 3:
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| 245 |
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| 246 | cmpwi 0, r5, 0
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| 247 | beqlr
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| 248 | mtctr r5
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| 249 | addi r4, r4, 3
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| 250 | addi r6, r6, 3
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| 251 |
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| 252 | 4:
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| 253 |
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| 254 | lbzu r0, 1(r4)
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| 255 | stbu r0, 1(r6)
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| 256 | bdnz 4b
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| [393f631] | 257 | blr
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| [6f8a426] | 258 |
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| 259 | 5:
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| 260 |
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| 261 | subfic r0, r0, 4
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| 262 | mtctr r0
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| 263 |
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| 264 | 6:
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| 265 |
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| 266 | lbz r7, 4(r4)
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| 267 | addi r4, r4, 1
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| 268 | stb r7, 4(r6)
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| 269 | addi r6, r6, 1
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| 270 | bdnz 6b
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| 271 | subf r5, r0, r5
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| 272 | rlwinm. r7, r5, 32-3, 3, 31
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| 273 | beq 2b
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| 274 | mtctr r7
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| 275 | b 1b
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| [e3c762cd] | 276 |
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| 277 | memcpy_from_uspace_failover_address:
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| 278 | memcpy_to_uspace_failover_address:
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| [ac0e791] | 279 | # return zero, failure
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| 280 | xor r3, r3, r3
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| 281 | blr
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