source: mainline/kernel/arch/ppc32/src/asm.S@ c39544a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c39544a was da52547, checked in by Martin Decky <martin@…>, 15 years ago

add early_putchar() which can be used to do early kernel console output for debugging purposes
(the availability of this feature depends on each platform and specific configuration, currently it works only on ia32/amd64 with EGA and no framebuffer)
instrument more kernel functions
mark some functions as no_instrument (context_restore(), overlaps(), main_bsp())
  • Property mode set to 100644
File size: 4.7 KB
RevLine 
[eedf4c5]1/*
2 * Copyright (c) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[efa9b73]28
[37c8975]29#include <arch/asm/regname.h>
[ffe276f]30#include <arch/cpu.h>
[10caad0]31
[efa9b73]32.text
33
[e692a27]34.global userspace_asm
[91d5ad6]35.global iret
[e34a141]36.global iret_syscall
[393f631]37.global memsetb
[b60c582]38.global memsetw
[393f631]39.global memcpy
[e3c762cd]40.global memcpy_from_uspace
41.global memcpy_to_uspace
42.global memcpy_from_uspace_failover_address
43.global memcpy_to_uspace_failover_address
[eedf4c5]44.global early_putchar
[dfbc229]45
[e692a27]46userspace_asm:
[ffe276f]47
[eedf4c5]48 /*
49 * r3 = uspace_uarg
50 * r4 = stack
51 * r5 = entry
52 */
[762a824]53
[eedf4c5]54 /* Disable interrupts */
[ffe276f]55
[e692a27]56 mfmsr r31
57 rlwinm r31, r31, 0, 17, 15
58 mtmsr r31
59
[eedf4c5]60 /* Set entry point */
[e692a27]61
62 mtsrr0 r5
63
[eedf4c5]64 /* Set problem state, enable interrupts */
[e692a27]65
[ffe276f]66 ori r31, r31, MSR_PR
67 ori r31, r31, MSR_EE
[e692a27]68 mtsrr1 r31
69
[eedf4c5]70 /* Set stack */
[e692a27]71
72 mr sp, r4
[ffe276f]73
[eedf4c5]74 /* %r6 is defined to hold pcb_ptr - set it to 0 */
[ffe276f]75
[c1b455e]76 xor r6, r6, r6
[e692a27]77
[eedf4c5]78 /* Jump to userspace */
[e692a27]79
80 rfi
81
[91d5ad6]82iret:
[e34a141]83
[eedf4c5]84 /* Disable interrupts */
[e34a141]85
86 mfmsr r31
87 rlwinm r31, r31, 0, 17, 15
88 mtmsr r31
89
[2e2d654]90 lwz r0, 8(sp)
91 lwz r2, 12(sp)
92 lwz r3, 16(sp)
93 lwz r4, 20(sp)
94 lwz r5, 24(sp)
95 lwz r6, 28(sp)
96 lwz r7, 32(sp)
97 lwz r8, 36(sp)
98 lwz r9, 40(sp)
99 lwz r10, 44(sp)
100 lwz r11, 48(sp)
101 lwz r13, 52(sp)
102 lwz r14, 56(sp)
103 lwz r15, 60(sp)
104 lwz r16, 64(sp)
105 lwz r17, 68(sp)
106 lwz r18, 72(sp)
107 lwz r19, 76(sp)
108 lwz r20, 80(sp)
109 lwz r21, 84(sp)
110 lwz r22, 88(sp)
111 lwz r23, 92(sp)
112 lwz r24, 96(sp)
113 lwz r25, 100(sp)
114 lwz r26, 104(sp)
115 lwz r27, 108(sp)
116 lwz r28, 112(sp)
117 lwz r29, 116(sp)
118 lwz r30, 120(sp)
119 lwz r31, 124(sp)
120
121 lwz r12, 128(sp)
[e34a141]122 mtcr r12
[762a824]123
[2e2d654]124 lwz r12, 132(sp)
[e34a141]125 mtsrr0 r12
[762a824]126
[2e2d654]127 lwz r12, 136(sp)
[e34a141]128 mtsrr1 r12
[762a824]129
[2e2d654]130 lwz r12, 140(sp)
[e34a141]131 mtlr r12
[762a824]132
[2e2d654]133 lwz r12, 144(sp)
[762a824]134 mtctr r12
135
[2e2d654]136 lwz r12, 148(sp)
[762a824]137 mtxer r12
[e34a141]138
[826c203]139 lwz r12, 156(sp)
140 lwz sp, 160(sp)
[e34a141]141
142 rfi
[762a824]143
[e34a141]144iret_syscall:
[91d5ad6]145
[eedf4c5]146 /* Reset decrementer */
[ffe276f]147
[a33c990]148 li r31, 1000
149 mtdec r31
150
[eedf4c5]151 /* Disable interrupts */
[e34a141]152
153 mfmsr r31
154 rlwinm r31, r31, 0, 17, 15
155 mtmsr r31
156
[2e2d654]157 lwz r0, 8(sp)
158 lwz r2, 12(sp)
159 lwz r4, 20(sp)
160 lwz r5, 24(sp)
161 lwz r6, 28(sp)
162 lwz r7, 32(sp)
163 lwz r8, 36(sp)
164 lwz r9, 40(sp)
165 lwz r10, 44(sp)
166 lwz r11, 48(sp)
167 lwz r13, 52(sp)
168 lwz r14, 56(sp)
169 lwz r15, 60(sp)
170 lwz r16, 64(sp)
171 lwz r17, 68(sp)
172 lwz r18, 72(sp)
173 lwz r19, 76(sp)
174 lwz r20, 80(sp)
175 lwz r21, 84(sp)
176 lwz r22, 88(sp)
177 lwz r23, 92(sp)
178 lwz r24, 96(sp)
179 lwz r25, 100(sp)
180 lwz r26, 104(sp)
181 lwz r27, 108(sp)
182 lwz r28, 112(sp)
183 lwz r29, 116(sp)
184 lwz r30, 120(sp)
185 lwz r31, 124(sp)
186
187 lwz r12, 128(sp)
[e34a141]188 mtcr r12
189
[2e2d654]190 lwz r12, 132(sp)
[e34a141]191 mtsrr0 r12
192
[2e2d654]193 lwz r12, 136(sp)
[e34a141]194 mtsrr1 r12
195
[2e2d654]196 lwz r12, 140(sp)
[e34a141]197 mtlr r12
198
[2e2d654]199 lwz r12, 144(sp)
[e34a141]200 mtctr r12
201
[2e2d654]202 lwz r12, 148(sp)
[e34a141]203 mtxer r12
204
[826c203]205 lwz r12, 156(sp)
206 lwz sp, 160(sp)
[ffe276f]207
[91d5ad6]208 rfi
[b60c582]209
[393f631]210memsetb:
[7560b606]211 b _memsetb
[393f631]212
[b60c582]213memsetw:
214 b _memsetw
215
[393f631]216memcpy:
[e3c762cd]217memcpy_from_uspace:
218memcpy_to_uspace:
[ffe276f]219
[6f8a426]220 srwi. r7, r5, 3
221 addi r6, r3, -4
222 addi r4, r4, -4
[ffe276f]223 beq 2f
[6f8a426]224
225 andi. r0, r6, 3
226 mtctr r7
227 bne 5f
228
229 1:
230
[ffe276f]231 lwz r7, 4(r4)
232 lwzu r8, 8(r4)
233 stw r7, 4(r6)
234 stwu r8, 8(r6)
235 bdnz 1b
236
237 andi. r5, r5, 7
[6f8a426]238
239 2:
240
[ffe276f]241 cmplwi 0, r5, 4
242 blt 3f
243
244 lwzu r0, 4(r4)
245 addi r5, r5, -4
246 stwu r0, 4(r6)
[6f8a426]247
248 3:
249
[ffe276f]250 cmpwi 0, r5, 0
251 beqlr
252 mtctr r5
253 addi r4, r4, 3
254 addi r6, r6, 3
[6f8a426]255
256 4:
257
[ffe276f]258 lbzu r0, 1(r4)
259 stbu r0, 1(r6)
260 bdnz 4b
261 blr
[6f8a426]262
263 5:
264
[ffe276f]265 subfic r0, r0, 4
266 mtctr r0
[6f8a426]267
268 6:
269
[ffe276f]270 lbz r7, 4(r4)
271 addi r4, r4, 1
272 stb r7, 4(r6)
273 addi r6, r6, 1
274 bdnz 6b
275 subf r5, r0, r5
276 rlwinm. r7, r5, 32-3, 3, 31
277 beq 2b
278 mtctr r7
279 b 1b
[e3c762cd]280
281memcpy_from_uspace_failover_address:
282memcpy_to_uspace_failover_address:
[eedf4c5]283 /* Return zero, failure */
[ac0e791]284 xor r3, r3, r3
285 blr
[da52547]286
287early_putchar:
288 blr
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