| [efa9b73] | 1 | #
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| [df4ed85] | 2 | # Copyright (c) 2005 Martin Decky
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| [efa9b73] | 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| [37c8975] | 29 | #include <arch/asm/regname.h>
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| [10caad0] | 30 |
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| [efa9b73] | 31 | .text
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| 32 |
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| [e692a27] | 33 | .global userspace_asm
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| [91d5ad6] | 34 | .global iret
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| [e34a141] | 35 | .global iret_syscall
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| [393f631] | 36 | .global memsetb
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| 37 | .global memcpy
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| [e3c762cd] | 38 | .global memcpy_from_uspace
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| 39 | .global memcpy_to_uspace
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| 40 | .global memcpy_from_uspace_failover_address
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| 41 | .global memcpy_to_uspace_failover_address
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| [dfbc229] | 42 |
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| [e692a27] | 43 | userspace_asm:
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| 44 |
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| 45 | # r3 = uspace_uarg
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| 46 | # r4 = stack
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| [762a824] | 47 | # r5 = entry
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| 48 |
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| 49 | # disable interrupts
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| [e692a27] | 50 |
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| 51 | mfmsr r31
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| 52 | rlwinm r31, r31, 0, 17, 15
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| 53 | mtmsr r31
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| 54 |
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| 55 | # set entry point
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| 56 |
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| 57 | mtsrr0 r5
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| 58 |
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| 59 | # set problem state, enable interrupts
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| 60 |
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| [762a824] | 61 | ori r31, r31, msr_pr
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| 62 | ori r31, r31, msr_ee
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| [e692a27] | 63 | mtsrr1 r31
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| 64 |
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| 65 | # set stack
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| 66 |
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| 67 | mr sp, r4
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| [c98e6ee] | 68 |
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| [c1b455e] | 69 | # %r6 is defined to hold pcb_ptr - set it to 0
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| [c98e6ee] | 70 |
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| [c1b455e] | 71 | xor r6, r6, r6
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| [e692a27] | 72 |
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| 73 | # jump to userspace
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| 74 |
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| 75 | rfi
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| 76 |
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| [91d5ad6] | 77 | iret:
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| [e34a141] | 78 |
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| 79 | # disable interrupts
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| 80 |
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| 81 | mfmsr r31
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| 82 | rlwinm r31, r31, 0, 17, 15
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| 83 | mtmsr r31
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| 84 |
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| [2e2d654] | 85 | lwz r0, 8(sp)
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| 86 | lwz r2, 12(sp)
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| 87 | lwz r3, 16(sp)
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| 88 | lwz r4, 20(sp)
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| 89 | lwz r5, 24(sp)
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| 90 | lwz r6, 28(sp)
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| 91 | lwz r7, 32(sp)
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| 92 | lwz r8, 36(sp)
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| 93 | lwz r9, 40(sp)
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| 94 | lwz r10, 44(sp)
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| 95 | lwz r11, 48(sp)
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| 96 | lwz r13, 52(sp)
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| 97 | lwz r14, 56(sp)
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| 98 | lwz r15, 60(sp)
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| 99 | lwz r16, 64(sp)
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| 100 | lwz r17, 68(sp)
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| 101 | lwz r18, 72(sp)
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| 102 | lwz r19, 76(sp)
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| 103 | lwz r20, 80(sp)
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| 104 | lwz r21, 84(sp)
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| 105 | lwz r22, 88(sp)
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| 106 | lwz r23, 92(sp)
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| 107 | lwz r24, 96(sp)
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| 108 | lwz r25, 100(sp)
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| 109 | lwz r26, 104(sp)
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| 110 | lwz r27, 108(sp)
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| 111 | lwz r28, 112(sp)
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| 112 | lwz r29, 116(sp)
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| 113 | lwz r30, 120(sp)
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| 114 | lwz r31, 124(sp)
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| 115 |
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| 116 | lwz r12, 128(sp)
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| [e34a141] | 117 | mtcr r12
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| [762a824] | 118 |
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| [2e2d654] | 119 | lwz r12, 132(sp)
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| [e34a141] | 120 | mtsrr0 r12
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| [762a824] | 121 |
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| [2e2d654] | 122 | lwz r12, 136(sp)
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| [e34a141] | 123 | mtsrr1 r12
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| [762a824] | 124 |
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| [2e2d654] | 125 | lwz r12, 140(sp)
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| [e34a141] | 126 | mtlr r12
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| [762a824] | 127 |
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| [2e2d654] | 128 | lwz r12, 144(sp)
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| [762a824] | 129 | mtctr r12
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| 130 |
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| [2e2d654] | 131 | lwz r12, 148(sp)
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| [762a824] | 132 | mtxer r12
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| [e34a141] | 133 |
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| [2e2d654] | 134 | lwz r12, 152(sp)
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| 135 | lwz sp, 156(sp)
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| [e34a141] | 136 |
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| 137 | rfi
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| [762a824] | 138 |
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| [e34a141] | 139 | iret_syscall:
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| [91d5ad6] | 140 |
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| [a33c990] | 141 | # reset decrementer
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| 142 |
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| 143 | li r31, 1000
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| 144 | mtdec r31
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| 145 |
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| [e34a141] | 146 | # disable interrupts
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| 147 |
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| 148 | mfmsr r31
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| 149 | rlwinm r31, r31, 0, 17, 15
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| 150 | mtmsr r31
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| 151 |
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| [2e2d654] | 152 | lwz r0, 8(sp)
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| 153 | lwz r2, 12(sp)
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| 154 | lwz r4, 20(sp)
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| 155 | lwz r5, 24(sp)
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| 156 | lwz r6, 28(sp)
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| 157 | lwz r7, 32(sp)
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| 158 | lwz r8, 36(sp)
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| 159 | lwz r9, 40(sp)
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| 160 | lwz r10, 44(sp)
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| 161 | lwz r11, 48(sp)
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| 162 | lwz r13, 52(sp)
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| 163 | lwz r14, 56(sp)
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| 164 | lwz r15, 60(sp)
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| 165 | lwz r16, 64(sp)
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| 166 | lwz r17, 68(sp)
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| 167 | lwz r18, 72(sp)
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| 168 | lwz r19, 76(sp)
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| 169 | lwz r20, 80(sp)
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| 170 | lwz r21, 84(sp)
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| 171 | lwz r22, 88(sp)
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| 172 | lwz r23, 92(sp)
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| 173 | lwz r24, 96(sp)
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| 174 | lwz r25, 100(sp)
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| 175 | lwz r26, 104(sp)
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| 176 | lwz r27, 108(sp)
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| 177 | lwz r28, 112(sp)
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| 178 | lwz r29, 116(sp)
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| 179 | lwz r30, 120(sp)
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| 180 | lwz r31, 124(sp)
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| 181 |
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| 182 | lwz r12, 128(sp)
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| [e34a141] | 183 | mtcr r12
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| 184 |
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| [2e2d654] | 185 | lwz r12, 132(sp)
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| [e34a141] | 186 | mtsrr0 r12
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| 187 |
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| [2e2d654] | 188 | lwz r12, 136(sp)
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| [e34a141] | 189 | mtsrr1 r12
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| 190 |
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| [2e2d654] | 191 | lwz r12, 140(sp)
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| [e34a141] | 192 | mtlr r12
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| 193 |
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| [2e2d654] | 194 | lwz r12, 144(sp)
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| [e34a141] | 195 | mtctr r12
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| 196 |
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| [2e2d654] | 197 | lwz r12, 148(sp)
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| [e34a141] | 198 | mtxer r12
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| 199 |
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| [2e2d654] | 200 | lwz r12, 152(sp)
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| 201 | lwz sp, 156(sp)
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| [e34a141] | 202 |
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| [91d5ad6] | 203 | rfi
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| 204 |
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| [393f631] | 205 | memsetb:
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| [7560b606] | 206 | b _memsetb
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| [393f631] | 207 |
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| 208 | memcpy:
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| [e3c762cd] | 209 | memcpy_from_uspace:
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| 210 | memcpy_to_uspace:
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| 211 |
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| [6f8a426] | 212 | srwi. r7, r5, 3
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| 213 | addi r6, r3, -4
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| 214 | addi r4, r4, -4
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| 215 | beq 2f
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| 216 |
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| 217 | andi. r0, r6, 3
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| 218 | mtctr r7
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| 219 | bne 5f
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| 220 |
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| 221 | 1:
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| 222 |
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| 223 | lwz r7, 4(r4)
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| 224 | lwzu r8, 8(r4)
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| 225 | stw r7, 4(r6)
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| 226 | stwu r8, 8(r6)
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| 227 | bdnz 1b
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| 228 |
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| 229 | andi. r5, r5, 7
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| 230 |
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| 231 | 2:
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| 232 |
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| 233 | cmplwi 0, r5, 4
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| 234 | blt 3f
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| 235 |
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| 236 | lwzu r0, 4(r4)
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| 237 | addi r5, r5, -4
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| 238 | stwu r0, 4(r6)
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| 239 |
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| 240 | 3:
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| 241 |
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| 242 | cmpwi 0, r5, 0
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| 243 | beqlr
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| 244 | mtctr r5
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| 245 | addi r4, r4, 3
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| 246 | addi r6, r6, 3
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| 247 |
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| 248 | 4:
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| 249 |
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| 250 | lbzu r0, 1(r4)
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| 251 | stbu r0, 1(r6)
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| 252 | bdnz 4b
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| [393f631] | 253 | blr
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| [6f8a426] | 254 |
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| 255 | 5:
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| 256 |
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| 257 | subfic r0, r0, 4
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| 258 | mtctr r0
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| 259 |
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| 260 | 6:
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| 261 |
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| 262 | lbz r7, 4(r4)
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| 263 | addi r4, r4, 1
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| 264 | stb r7, 4(r6)
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| 265 | addi r6, r6, 1
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| 266 | bdnz 6b
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| 267 | subf r5, r0, r5
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| 268 | rlwinm. r7, r5, 32-3, 3, 31
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| 269 | beq 2b
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| 270 | mtctr r7
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| 271 | b 1b
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| [e3c762cd] | 272 |
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| 273 | memcpy_from_uspace_failover_address:
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| 274 | memcpy_to_uspace_failover_address:
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| [ac0e791] | 275 | # return zero, failure
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| 276 | xor r3, r3, r3
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| 277 | blr
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