1 | /*
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2 | * Copyright (c) 2005 Martin Decky
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** @addtogroup ppc32
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30 | * @{
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31 | */
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32 | /** @file
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33 | */
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34 |
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35 | #ifndef KERN_ppc32_ASM_H_
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36 | #define KERN_ppc32_ASM_H_
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37 |
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38 | #include <typedefs.h>
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39 | #include <config.h>
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40 | #include <arch/cpu.h>
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41 |
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42 | static inline uint32_t msr_read(void)
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43 | {
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44 | uint32_t msr;
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45 |
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46 | asm volatile (
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47 | "mfmsr %[msr]\n"
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48 | : [msr] "=r" (msr)
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49 | );
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50 |
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51 | return msr;
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52 | }
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53 |
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54 | static inline void msr_write(uint32_t msr)
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55 | {
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56 | asm volatile (
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57 | "mtmsr %[msr]\n"
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58 | :: [msr] "r" (msr)
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59 | );
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60 | }
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61 |
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62 | static inline uint32_t msr_read(void)
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63 | {
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64 | uint32_t msr;
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65 |
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66 | asm volatile (
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67 | "mfmsr %[msr]\n"
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68 | : [msr] "=r" (msr)
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69 | );
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70 |
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71 | return msr;
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72 | }
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73 |
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74 | static inline void msr_write(uint32_t msr)
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75 | {
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76 | asm volatile (
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77 | "mtmsr %[msr]\n"
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78 | :: [msr] "r" (msr)
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79 | );
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80 | }
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81 |
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82 | /** Enable interrupts.
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83 | *
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84 | * Enable interrupts and return previous
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85 | * value of EE.
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86 | *
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87 | * @return Old interrupt priority level.
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88 | *
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89 | */
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90 | static inline ipl_t interrupts_enable(void)
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91 | {
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92 | ipl_t ipl = msr_read();
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93 | msr_write(ipl | MSR_EE);
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94 | return ipl;
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95 | }
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96 |
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97 | /** Disable interrupts.
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98 | *
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99 | * Disable interrupts and return previous
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100 | * value of EE.
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101 | *
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102 | * @return Old interrupt priority level.
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103 | *
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104 | */
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105 | static inline ipl_t interrupts_disable(void)
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106 | {
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107 | ipl_t ipl = msr_read();
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108 | msr_write(ipl & (~MSR_EE));
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109 | return ipl;
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110 | }
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111 |
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112 | /** Restore interrupt priority level.
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113 | *
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114 | * Restore EE.
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115 | *
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116 | * @param ipl Saved interrupt priority level.
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117 | *
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118 | */
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119 | static inline void interrupts_restore(ipl_t ipl)
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120 | {
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121 | msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE));
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122 | }
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123 |
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124 | /** Return interrupt priority level.
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125 | *
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126 | * Return EE.
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127 | *
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128 | * @return Current interrupt priority level.
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129 | *
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130 | */
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131 | static inline ipl_t interrupts_read(void)
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132 | {
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133 | return msr_read();
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134 | }
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135 |
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136 | /** Check whether interrupts are disabled.
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137 | *
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138 | * @return True if interrupts are disabled.
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139 | *
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140 | */
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141 | static inline bool interrupts_disabled(void)
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142 | {
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143 | return ((msr_read() & MSR_EE) == 0);
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144 | }
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145 |
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146 | /** Return base address of current stack.
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147 | *
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148 | * Return the base address of the current stack.
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149 | * The stack is assumed to be STACK_SIZE bytes long.
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150 | * The stack must start on page boundary.
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151 | *
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152 | */
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153 | static inline uintptr_t get_stack_base(void)
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154 | {
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155 | uintptr_t base;
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156 |
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157 | asm volatile (
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158 | "and %[base], %%sp, %[mask]\n"
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159 | : [base] "=r" (base)
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160 | : [mask] "r" (~(STACK_SIZE - 1))
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161 | );
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162 |
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163 | return base;
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164 | }
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165 |
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166 | static inline void cpu_sleep(void)
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167 | {
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168 | }
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169 |
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170 | extern void cpu_halt(void) __attribute__((noreturn));
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171 | extern void asm_delay_loop(uint32_t t);
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172 | extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry);
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173 |
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174 | static inline void pio_write_8(ioport8_t *port, uint8_t v)
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175 | {
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176 | *port = v;
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177 | }
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178 |
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179 | static inline void pio_write_16(ioport16_t *port, uint16_t v)
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180 | {
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181 | *port = v;
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182 | }
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183 |
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184 | static inline void pio_write_32(ioport32_t *port, uint32_t v)
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185 | {
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186 | *port = v;
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187 | }
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188 |
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189 | static inline uint8_t pio_read_8(ioport8_t *port)
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190 | {
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191 | return *port;
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192 | }
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193 |
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194 | static inline uint16_t pio_read_16(ioport16_t *port)
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195 | {
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196 | return *port;
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197 | }
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198 |
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199 | static inline uint32_t pio_read_32(ioport32_t *port)
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200 | {
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201 | return *port;
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202 | }
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203 |
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204 | #endif
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205 |
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206 | /** @}
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207 | */
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