source: mainline/kernel/arch/ppc32/include/asm.h@ 8263c68

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8263c68 was c22e964, checked in by Jakub Jermar <jakub@…>, 16 years ago

There is no need to define ioport{8,16,32}_t types for each architecture separately.

  • Property mode set to 100644
File size: 3.8 KB
RevLine 
[361635c]1/*
[df4ed85]2 * Copyright (c) 2005 Martin Decky
[361635c]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ppc32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_ppc32_ASM_H_
36#define KERN_ppc32_ASM_H_
[361635c]37
38#include <arch/types.h>
[c22e964]39#include <typedefs.h>
[361635c]40#include <config.h>
41
[22f7769]42/** Enable interrupts.
[10caad0]43 *
44 * Enable interrupts and return previous
45 * value of EE.
[22f7769]46 *
47 * @return Old interrupt priority level.
[10caad0]48 */
[cc35e88]49static inline ipl_t interrupts_enable(void)
50{
[16dad032]51 ipl_t v;
[22f7769]52 ipl_t tmp;
[fe56609d]53
[762a824]54 asm volatile (
[3de9e5e]55 "mfmsr %0\n"
[fe56609d]56 "mfmsr %1\n"
[edc89bd0]57 "ori %1, %1, 1 << 15\n"
[fe56609d]58 "mtmsr %1\n"
59 : "=r" (v), "=r" (tmp)
[10caad0]60 );
61 return v;
62}
63
[22f7769]64/** Disable interrupts.
[10caad0]65 *
66 * Disable interrupts and return previous
67 * value of EE.
[22f7769]68 *
69 * @return Old interrupt priority level.
[10caad0]70 */
[cc35e88]71static inline ipl_t interrupts_disable(void)
72{
[22f7769]73 ipl_t v;
74 ipl_t tmp;
[fe56609d]75
[762a824]76 asm volatile (
[3de9e5e]77 "mfmsr %0\n"
[fe56609d]78 "mfmsr %1\n"
79 "rlwinm %1, %1, 0, 17, 15\n"
80 "mtmsr %1\n"
81 : "=r" (v), "=r" (tmp)
[10caad0]82 );
83 return v;
84}
85
[22f7769]86/** Restore interrupt priority level.
[10caad0]87 *
88 * Restore EE.
[22f7769]89 *
90 * @param ipl Saved interrupt priority level.
[10caad0]91 */
[cc35e88]92static inline void interrupts_restore(ipl_t ipl)
93{
[22f7769]94 ipl_t tmp;
[fe56609d]95
[762a824]96 asm volatile (
[fe56609d]97 "mfmsr %1\n"
98 "rlwimi %0, %1, 0, 17, 15\n"
99 "cmpw 0, %0, %1\n"
[393f631]100 "beq 0f\n"
[3de9e5e]101 "mtmsr %0\n"
[393f631]102 "0:\n"
[22f7769]103 : "=r" (ipl), "=r" (tmp)
104 : "0" (ipl)
[cc35e88]105 : "cr0"
[10caad0]106 );
107}
108
[22f7769]109/** Return interrupt priority level.
[393f631]110 *
111 * Return EE.
[22f7769]112 *
113 * @return Current interrupt priority level.
[393f631]114 */
[cc35e88]115static inline ipl_t interrupts_read(void)
116{
[22f7769]117 ipl_t v;
[762a824]118
119 asm volatile (
[393f631]120 "mfmsr %0\n"
121 : "=r" (v)
122 );
123 return v;
124}
125
[82a80d3]126/** Return base address of current stack.
127 *
128 * Return the base address of the current stack.
129 * The stack is assumed to be STACK_SIZE bytes long.
130 * The stack must start on page boundary.
131 */
[7f1c620]132static inline uintptr_t get_stack_base(void)
[361635c]133{
[7f1c620]134 uintptr_t v;
[82a80d3]135
[762a824]136 asm volatile (
137 "and %0, %%sp, %1\n"
138 : "=r" (v)
139 : "r" (~(STACK_SIZE - 1))
140 );
[82a80d3]141 return v;
[361635c]142}
143
[8965838e]144static inline void cpu_sleep(void)
145{
146}
147
[fe56609d]148void cpu_halt(void);
[7f1c620]149void asm_delay_loop(uint32_t t);
[c5ae095]150
[7f1c620]151extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry);
[e692a27]152
[7d60cf5]153static inline void pio_write_8(ioport8_t *port, uint8_t v)
[6da1013f]154{
[e78136a]155 *port = v;
156}
157
158static inline void pio_write_16(ioport16_t *port, uint16_t v)
159{
160 *port = v;
161}
162
163static inline void pio_write_32(ioport32_t *port, uint32_t v)
164{
165 *port = v;
[6da1013f]166}
167
[7d60cf5]168static inline uint8_t pio_read_8(ioport8_t *port)
[6da1013f]169{
[e78136a]170 return *port;
171}
172
173static inline uint16_t pio_read_16(ioport16_t *port)
174{
175 return *port;
176}
177
178static inline uint32_t pio_read_32(ioport32_t *port)
179{
180 return *port;
[6da1013f]181}
182
[361635c]183#endif
[b45c443]184
[06e1e95]185/** @}
[b45c443]186 */
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