source: mainline/kernel/arch/mips32/src/mm/tlb.c@ cf538e7

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cf538e7 was cf538e7, checked in by Jakub Jermar <jakub@…>, 13 years ago

Behaviour of the TLB invalid exception is different on 4Kc than on R4000.
  • Property mode set to 100644
File size: 9.7 KB
Line 
1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tlb.h>
36#include <mm/asid.h>
37#include <mm/tlb.h>
38#include <mm/page.h>
39#include <mm/as.h>
40#include <arch/cp0.h>
41#include <panic.h>
42#include <arch.h>
43#include <synch/mutex.h>
44#include <print.h>
45#include <debug.h>
46#include <align.h>
47#include <interrupt.h>
48#include <symtab.h>
49
50static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *);
51
52/** Initialize TLB.
53 *
54 * Invalidate all entries and mark wired entries.
55 */
56void tlb_arch_init(void)
57{
58 int i;
59
60 cp0_pagemask_write(TLB_PAGE_MASK_16K);
61 cp0_entry_hi_write(0);
62 cp0_entry_lo0_write(0);
63 cp0_entry_lo1_write(0);
64
65 /* Clear and initialize TLB. */
66
67 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
68 cp0_index_write(i);
69 tlbwi();
70 }
71
72 /*
73 * The kernel is going to make use of some wired
74 * entries (e.g. mapping kernel stacks in kseg3).
75 */
76 cp0_wired_write(TLB_WIRED);
77}
78
79/** Process TLB Refill Exception.
80 *
81 * @param istate Interrupted register context.
82 */
83void tlb_refill(istate_t *istate)
84{
85 entry_lo_t lo;
86 entry_hi_t hi;
87 asid_t asid;
88 uintptr_t badvaddr;
89 pte_t *pte;
90
91 badvaddr = cp0_badvaddr_read();
92 asid = AS->asid;
93
94 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
95 if (pte) {
96 /*
97 * Record access to PTE.
98 */
99 pte->a = 1;
100
101 tlb_prepare_entry_hi(&hi, asid, badvaddr);
102 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d,
103 pte->cacheable, pte->pfn);
104
105 /*
106 * New entry is to be inserted into TLB
107 */
108 cp0_entry_hi_write(hi.value);
109 if ((badvaddr / PAGE_SIZE) % 2 == 0) {
110 cp0_entry_lo0_write(lo.value);
111 cp0_entry_lo1_write(0);
112 } else {
113 cp0_entry_lo0_write(0);
114 cp0_entry_lo1_write(lo.value);
115 }
116 cp0_pagemask_write(TLB_PAGE_MASK_16K);
117 tlbwr();
118 }
119}
120
121/** Process TLB Invalid Exception.
122 *
123 * @param istate Interrupted register context.
124 */
125void tlb_invalid(istate_t *istate)
126{
127 tlb_index_t index;
128 uintptr_t badvaddr;
129 entry_lo_t lo;
130 entry_hi_t hi;
131 pte_t *pte;
132
133 badvaddr = cp0_badvaddr_read();
134
135 /*
136 * Locate the faulting entry in TLB.
137 */
138 hi.value = cp0_entry_hi_read();
139 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
140 cp0_entry_hi_write(hi.value);
141 tlbp();
142 index.value = cp0_index_read();
143
144#if defined(PROCESSOR_4Kc)
145 /*
146 * This can happen on a 4Kc when Status.EXL is 1 and there is a TLB miss.
147 * EXL is 1 when interrupts are disabled. The combination of a TLB miss
148 * and disabled interrupts is possible in copy_to/from_uspace().
149 */
150 if (index.p) {
151 tlb_refill(istate);
152 return;
153 }
154#endif
155
156 ASSERT(!index.p);
157
158 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
159 if (pte) {
160 /*
161 * Read the faulting TLB entry.
162 */
163 tlbr();
164
165 /*
166 * Record access to PTE.
167 */
168 pte->a = 1;
169
170 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d,
171 pte->cacheable, pte->pfn);
172
173 /*
174 * The entry is to be updated in TLB.
175 */
176 if ((badvaddr / PAGE_SIZE) % 2 == 0)
177 cp0_entry_lo0_write(lo.value);
178 else
179 cp0_entry_lo1_write(lo.value);
180 cp0_pagemask_write(TLB_PAGE_MASK_16K);
181 tlbwi();
182 }
183}
184
185/** Process TLB Modified Exception.
186 *
187 * @param istate Interrupted register context.
188 */
189void tlb_modified(istate_t *istate)
190{
191 tlb_index_t index;
192 uintptr_t badvaddr;
193 entry_lo_t lo;
194 entry_hi_t hi;
195 pte_t *pte;
196
197 badvaddr = cp0_badvaddr_read();
198
199 /*
200 * Locate the faulting entry in TLB.
201 */
202 hi.value = cp0_entry_hi_read();
203 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
204 cp0_entry_hi_write(hi.value);
205 tlbp();
206 index.value = cp0_index_read();
207
208 /*
209 * Fail if the entry is not in TLB.
210 */
211 ASSERT(!index.p);
212
213 pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate);
214 if (pte) {
215 /*
216 * Read the faulting TLB entry.
217 */
218 tlbr();
219
220 /*
221 * Record access and write to PTE.
222 */
223 pte->a = 1;
224 pte->d = 1;
225
226 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w,
227 pte->cacheable, pte->pfn);
228
229 /*
230 * The entry is to be updated in TLB.
231 */
232 if ((badvaddr / PAGE_SIZE) % 2 == 0)
233 cp0_entry_lo0_write(lo.value);
234 else
235 cp0_entry_lo1_write(lo.value);
236 cp0_pagemask_write(TLB_PAGE_MASK_16K);
237 tlbwi();
238 }
239}
240
241/** Try to find PTE for faulting address.
242 *
243 * @param badvaddr Faulting virtual address.
244 * @param access Access mode that caused the fault.
245 * @param istate Pointer to interrupted state.
246 *
247 * @return PTE on success, NULL otherwise.
248 */
249pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate)
250{
251 entry_hi_t hi;
252 pte_t *pte;
253
254 hi.value = cp0_entry_hi_read();
255
256 ASSERT(hi.asid == AS->asid);
257
258 /*
259 * Check if the mapping exists in page tables.
260 */
261 pte = page_mapping_find(AS, badvaddr, true);
262 if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
263 /*
264 * Mapping found in page tables.
265 * Immediately succeed.
266 */
267 return pte;
268 }
269
270 /*
271 * Mapping not found in page tables.
272 * Resort to higher-level page fault handler.
273 */
274 if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) {
275 pte = page_mapping_find(AS, badvaddr, true);
276 ASSERT(pte && pte->p);
277 ASSERT(pte->w || access != PF_ACCESS_WRITE);
278 return pte;
279 }
280
281 return NULL;
282}
283
284void
285tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
286 uintptr_t pfn)
287{
288 lo->value = 0;
289 lo->g = g;
290 lo->v = v;
291 lo->d = d;
292 lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
293 lo->pfn = pfn;
294}
295
296void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
297{
298 hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
299 hi->asid = asid;
300}
301
302/** Print contents of TLB. */
303void tlb_print(void)
304{
305 page_mask_t mask;
306 entry_lo_t lo0, lo1;
307 entry_hi_t hi, hi_save;
308 unsigned int i;
309
310 hi_save.value = cp0_entry_hi_read();
311
312 printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n");
313
314 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
315 cp0_index_write(i);
316 tlbr();
317
318 mask.value = cp0_pagemask_read();
319 hi.value = cp0_entry_hi_read();
320 lo0.value = cp0_entry_lo0_read();
321 lo1.value = cp0_entry_lo1_read();
322
323 printf("%-4u %-6u %#6x %#6x %1u%1u%1u%1u %#6x\n",
324 i, hi.asid, hi.vpn2, mask.mask,
325 lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
326 printf(" %1u%1u%1u%1u %#6x\n",
327 lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
328 }
329
330 cp0_entry_hi_write(hi_save.value);
331}
332
333/** Invalidate all not wired TLB entries. */
334void tlb_invalidate_all(void)
335{
336 ipl_t ipl;
337 entry_lo_t lo0, lo1;
338 entry_hi_t hi_save;
339 int i;
340
341 hi_save.value = cp0_entry_hi_read();
342 ipl = interrupts_disable();
343
344 for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
345 cp0_index_write(i);
346 tlbr();
347
348 lo0.value = cp0_entry_lo0_read();
349 lo1.value = cp0_entry_lo1_read();
350
351 lo0.v = 0;
352 lo1.v = 0;
353
354 cp0_entry_lo0_write(lo0.value);
355 cp0_entry_lo1_write(lo1.value);
356
357 tlbwi();
358 }
359
360 interrupts_restore(ipl);
361 cp0_entry_hi_write(hi_save.value);
362}
363
364/** Invalidate all TLB entries belonging to specified address space.
365 *
366 * @param asid Address space identifier.
367 */
368void tlb_invalidate_asid(asid_t asid)
369{
370 ipl_t ipl;
371 entry_lo_t lo0, lo1;
372 entry_hi_t hi, hi_save;
373 int i;
374
375 ASSERT(asid != ASID_INVALID);
376
377 hi_save.value = cp0_entry_hi_read();
378 ipl = interrupts_disable();
379
380 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
381 cp0_index_write(i);
382 tlbr();
383
384 hi.value = cp0_entry_hi_read();
385
386 if (hi.asid == asid) {
387 lo0.value = cp0_entry_lo0_read();
388 lo1.value = cp0_entry_lo1_read();
389
390 lo0.v = 0;
391 lo1.v = 0;
392
393 cp0_entry_lo0_write(lo0.value);
394 cp0_entry_lo1_write(lo1.value);
395
396 tlbwi();
397 }
398 }
399
400 interrupts_restore(ipl);
401 cp0_entry_hi_write(hi_save.value);
402}
403
404/** Invalidate TLB entries for specified page range belonging to specified
405 * address space.
406 *
407 * @param asid Address space identifier.
408 * @param page First page whose TLB entry is to be invalidated.
409 * @param cnt Number of entries to invalidate.
410 */
411void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
412{
413 unsigned int i;
414 ipl_t ipl;
415 entry_lo_t lo0, lo1;
416 entry_hi_t hi, hi_save;
417 tlb_index_t index;
418
419 if (asid == ASID_INVALID)
420 return;
421
422 hi_save.value = cp0_entry_hi_read();
423 ipl = interrupts_disable();
424
425 for (i = 0; i < cnt + 1; i += 2) {
426 hi.value = 0;
427 tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
428 cp0_entry_hi_write(hi.value);
429
430 tlbp();
431 index.value = cp0_index_read();
432
433 if (!index.p) {
434 /*
435 * Entry was found, index register contains valid
436 * index.
437 */
438 tlbr();
439
440 lo0.value = cp0_entry_lo0_read();
441 lo1.value = cp0_entry_lo1_read();
442
443 lo0.v = 0;
444 lo1.v = 0;
445
446 cp0_entry_lo0_write(lo0.value);
447 cp0_entry_lo1_write(lo1.value);
448
449 tlbwi();
450 }
451 }
452
453 interrupts_restore(ipl);
454 cp0_entry_hi_write(hi_save.value);
455}
456
457/** @}
458 */
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