source: mainline/kernel/arch/mips32/src/mm/tlb.c@ 54a7a20

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 54a7a20 was 54a7a20, checked in by Martin Decky <martin@…>, 14 years ago

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1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tlb.h>
36#include <mm/asid.h>
37#include <mm/tlb.h>
38#include <mm/page.h>
39#include <mm/as.h>
40#include <arch/cp0.h>
41#include <panic.h>
42#include <arch.h>
43#include <synch/mutex.h>
44#include <print.h>
45#include <debug.h>
46#include <align.h>
47#include <interrupt.h>
48#include <symtab.h>
49
50static void tlb_refill_fail(istate_t *);
51static void tlb_invalid_fail(istate_t *);
52static void tlb_modified_fail(istate_t *);
53
54static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
55
56/** Initialize TLB.
57 *
58 * Invalidate all entries and mark wired entries.
59 */
60void tlb_arch_init(void)
61{
62 int i;
63
64 cp0_pagemask_write(TLB_PAGE_MASK_16K);
65 cp0_entry_hi_write(0);
66 cp0_entry_lo0_write(0);
67 cp0_entry_lo1_write(0);
68
69 /* Clear and initialize TLB. */
70
71 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
72 cp0_index_write(i);
73 tlbwi();
74 }
75
76 /*
77 * The kernel is going to make use of some wired
78 * entries (e.g. mapping kernel stacks in kseg3).
79 */
80 cp0_wired_write(TLB_WIRED);
81}
82
83/** Process TLB Refill Exception.
84 *
85 * @param istate Interrupted register context.
86 */
87void tlb_refill(istate_t *istate)
88{
89 entry_lo_t lo;
90 entry_hi_t hi;
91 asid_t asid;
92 uintptr_t badvaddr;
93 pte_t *pte;
94 int pfrc;
95
96 badvaddr = cp0_badvaddr_read();
97
98 mutex_lock(&AS->lock);
99 asid = AS->asid;
100 mutex_unlock(&AS->lock);
101
102 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
103 if (!pte) {
104 switch (pfrc) {
105 case AS_PF_FAULT:
106 goto fail;
107 break;
108 case AS_PF_DEFER:
109 /*
110 * The page fault came during copy_from_uspace()
111 * or copy_to_uspace().
112 */
113 return;
114 default:
115 panic("Unexpected pfrc (%d).", pfrc);
116 }
117 }
118
119 /*
120 * Record access to PTE.
121 */
122 pte->a = 1;
123
124 tlb_prepare_entry_hi(&hi, asid, badvaddr);
125 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
126 pte->pfn);
127
128 /*
129 * New entry is to be inserted into TLB
130 */
131 cp0_entry_hi_write(hi.value);
132 if ((badvaddr / PAGE_SIZE) % 2 == 0) {
133 cp0_entry_lo0_write(lo.value);
134 cp0_entry_lo1_write(0);
135 }
136 else {
137 cp0_entry_lo0_write(0);
138 cp0_entry_lo1_write(lo.value);
139 }
140 cp0_pagemask_write(TLB_PAGE_MASK_16K);
141 tlbwr();
142
143 return;
144
145fail:
146 tlb_refill_fail(istate);
147}
148
149/** Process TLB Invalid Exception.
150 *
151 * @param istate Interrupted register context.
152 */
153void tlb_invalid(istate_t *istate)
154{
155 tlb_index_t index;
156 uintptr_t badvaddr;
157 entry_lo_t lo;
158 entry_hi_t hi;
159 pte_t *pte;
160 int pfrc;
161
162 badvaddr = cp0_badvaddr_read();
163
164 /*
165 * Locate the faulting entry in TLB.
166 */
167 hi.value = cp0_entry_hi_read();
168 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
169 cp0_entry_hi_write(hi.value);
170 tlbp();
171 index.value = cp0_index_read();
172
173 /*
174 * Fail if the entry is not in TLB.
175 */
176 if (index.p) {
177 printf("TLB entry not found.\n");
178 goto fail;
179 }
180
181 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
182 if (!pte) {
183 switch (pfrc) {
184 case AS_PF_FAULT:
185 goto fail;
186 break;
187 case AS_PF_DEFER:
188 /*
189 * The page fault came during copy_from_uspace()
190 * or copy_to_uspace().
191 */
192 return;
193 default:
194 panic("Unexpected pfrc (%d).", pfrc);
195 }
196 }
197
198 /*
199 * Read the faulting TLB entry.
200 */
201 tlbr();
202
203 /*
204 * Record access to PTE.
205 */
206 pte->a = 1;
207
208 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
209 pte->pfn);
210
211 /*
212 * The entry is to be updated in TLB.
213 */
214 if ((badvaddr / PAGE_SIZE) % 2 == 0)
215 cp0_entry_lo0_write(lo.value);
216 else
217 cp0_entry_lo1_write(lo.value);
218 cp0_pagemask_write(TLB_PAGE_MASK_16K);
219 tlbwi();
220
221 return;
222
223fail:
224 tlb_invalid_fail(istate);
225}
226
227/** Process TLB Modified Exception.
228 *
229 * @param istate Interrupted register context.
230 */
231void tlb_modified(istate_t *istate)
232{
233 tlb_index_t index;
234 uintptr_t badvaddr;
235 entry_lo_t lo;
236 entry_hi_t hi;
237 pte_t *pte;
238 int pfrc;
239
240 badvaddr = cp0_badvaddr_read();
241
242 /*
243 * Locate the faulting entry in TLB.
244 */
245 hi.value = cp0_entry_hi_read();
246 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
247 cp0_entry_hi_write(hi.value);
248 tlbp();
249 index.value = cp0_index_read();
250
251 /*
252 * Fail if the entry is not in TLB.
253 */
254 if (index.p) {
255 printf("TLB entry not found.\n");
256 goto fail;
257 }
258
259 pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
260 if (!pte) {
261 switch (pfrc) {
262 case AS_PF_FAULT:
263 goto fail;
264 break;
265 case AS_PF_DEFER:
266 /*
267 * The page fault came during copy_from_uspace()
268 * or copy_to_uspace().
269 */
270 return;
271 default:
272 panic("Unexpected pfrc (%d).", pfrc);
273 }
274 }
275
276 /*
277 * Read the faulting TLB entry.
278 */
279 tlbr();
280
281 /*
282 * Record access and write to PTE.
283 */
284 pte->a = 1;
285 pte->d = 1;
286
287 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
288 pte->pfn);
289
290 /*
291 * The entry is to be updated in TLB.
292 */
293 if ((badvaddr / PAGE_SIZE) % 2 == 0)
294 cp0_entry_lo0_write(lo.value);
295 else
296 cp0_entry_lo1_write(lo.value);
297 cp0_pagemask_write(TLB_PAGE_MASK_16K);
298 tlbwi();
299
300 return;
301
302fail:
303 tlb_modified_fail(istate);
304}
305
306void tlb_refill_fail(istate_t *istate)
307{
308 uintptr_t va = cp0_badvaddr_read();
309
310 fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
311 (void *) va);
312 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception.");
313}
314
315
316void tlb_invalid_fail(istate_t *istate)
317{
318 uintptr_t va = cp0_badvaddr_read();
319
320 fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
321 (void *) va);
322 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception.");
323}
324
325void tlb_modified_fail(istate_t *istate)
326{
327 uintptr_t va = cp0_badvaddr_read();
328
329 fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
330 (void *) va);
331 panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception.");
332}
333
334/** Try to find PTE for faulting address.
335 *
336 * @param badvaddr Faulting virtual address.
337 * @param access Access mode that caused the fault.
338 * @param istate Pointer to interrupted state.
339 * @param pfrc Pointer to variable where as_page_fault() return code
340 * will be stored.
341 *
342 * @return PTE on success, NULL otherwise.
343 */
344pte_t *
345find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
346 int *pfrc)
347{
348 entry_hi_t hi;
349 pte_t *pte;
350
351 hi.value = cp0_entry_hi_read();
352
353 /*
354 * Handler cannot succeed if the ASIDs don't match.
355 */
356 if (hi.asid != AS->asid) {
357 printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
358 return NULL;
359 }
360
361 /*
362 * Check if the mapping exists in page tables.
363 */
364 pte = page_mapping_find(AS, badvaddr, true);
365 if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
366 /*
367 * Mapping found in page tables.
368 * Immediately succeed.
369 */
370 return pte;
371 } else {
372 int rc;
373
374 /*
375 * Mapping not found in page tables.
376 * Resort to higher-level page fault handler.
377 */
378 switch (rc = as_page_fault(badvaddr, access, istate)) {
379 case AS_PF_OK:
380 /*
381 * The higher-level page fault handler succeeded,
382 * The mapping ought to be in place.
383 */
384 pte = page_mapping_find(AS, badvaddr, true);
385 ASSERT(pte && pte->p);
386 ASSERT(pte->w || access != PF_ACCESS_WRITE);
387 return pte;
388 case AS_PF_DEFER:
389 *pfrc = AS_PF_DEFER;
390 return NULL;
391 case AS_PF_FAULT:
392 *pfrc = AS_PF_FAULT;
393 return NULL;
394 default:
395 panic("Unexpected rc (%d).", rc);
396 }
397
398 }
399}
400
401void
402tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
403 uintptr_t pfn)
404{
405 lo->value = 0;
406 lo->g = g;
407 lo->v = v;
408 lo->d = d;
409 lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
410 lo->pfn = pfn;
411}
412
413void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
414{
415 hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
416 hi->asid = asid;
417}
418
419/** Print contents of TLB. */
420void tlb_print(void)
421{
422 page_mask_t mask;
423 entry_lo_t lo0, lo1;
424 entry_hi_t hi, hi_save;
425 unsigned int i;
426
427 hi_save.value = cp0_entry_hi_read();
428
429 printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n");
430
431 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
432 cp0_index_write(i);
433 tlbr();
434
435 mask.value = cp0_pagemask_read();
436 hi.value = cp0_entry_hi_read();
437 lo0.value = cp0_entry_lo0_read();
438 lo1.value = cp0_entry_lo1_read();
439
440 printf("%-4u %-6u %#6x %#6x %1u%1u%1u%1u %#6x\n",
441 i, hi.asid, hi.vpn2, mask.mask,
442 lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
443 printf(" %1u%1u%1u%1u %#6x\n",
444 lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
445 }
446
447 cp0_entry_hi_write(hi_save.value);
448}
449
450/** Invalidate all not wired TLB entries. */
451void tlb_invalidate_all(void)
452{
453 ipl_t ipl;
454 entry_lo_t lo0, lo1;
455 entry_hi_t hi_save;
456 int i;
457
458 hi_save.value = cp0_entry_hi_read();
459 ipl = interrupts_disable();
460
461 for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
462 cp0_index_write(i);
463 tlbr();
464
465 lo0.value = cp0_entry_lo0_read();
466 lo1.value = cp0_entry_lo1_read();
467
468 lo0.v = 0;
469 lo1.v = 0;
470
471 cp0_entry_lo0_write(lo0.value);
472 cp0_entry_lo1_write(lo1.value);
473
474 tlbwi();
475 }
476
477 interrupts_restore(ipl);
478 cp0_entry_hi_write(hi_save.value);
479}
480
481/** Invalidate all TLB entries belonging to specified address space.
482 *
483 * @param asid Address space identifier.
484 */
485void tlb_invalidate_asid(asid_t asid)
486{
487 ipl_t ipl;
488 entry_lo_t lo0, lo1;
489 entry_hi_t hi, hi_save;
490 int i;
491
492 ASSERT(asid != ASID_INVALID);
493
494 hi_save.value = cp0_entry_hi_read();
495 ipl = interrupts_disable();
496
497 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
498 cp0_index_write(i);
499 tlbr();
500
501 hi.value = cp0_entry_hi_read();
502
503 if (hi.asid == asid) {
504 lo0.value = cp0_entry_lo0_read();
505 lo1.value = cp0_entry_lo1_read();
506
507 lo0.v = 0;
508 lo1.v = 0;
509
510 cp0_entry_lo0_write(lo0.value);
511 cp0_entry_lo1_write(lo1.value);
512
513 tlbwi();
514 }
515 }
516
517 interrupts_restore(ipl);
518 cp0_entry_hi_write(hi_save.value);
519}
520
521/** Invalidate TLB entries for specified page range belonging to specified
522 * address space.
523 *
524 * @param asid Address space identifier.
525 * @param page First page whose TLB entry is to be invalidated.
526 * @param cnt Number of entries to invalidate.
527 */
528void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
529{
530 unsigned int i;
531 ipl_t ipl;
532 entry_lo_t lo0, lo1;
533 entry_hi_t hi, hi_save;
534 tlb_index_t index;
535
536 if (asid == ASID_INVALID)
537 return;
538
539 hi_save.value = cp0_entry_hi_read();
540 ipl = interrupts_disable();
541
542 for (i = 0; i < cnt + 1; i += 2) {
543 hi.value = 0;
544 tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
545 cp0_entry_hi_write(hi.value);
546
547 tlbp();
548 index.value = cp0_index_read();
549
550 if (!index.p) {
551 /*
552 * Entry was found, index register contains valid
553 * index.
554 */
555 tlbr();
556
557 lo0.value = cp0_entry_lo0_read();
558 lo1.value = cp0_entry_lo1_read();
559
560 lo0.v = 0;
561 lo1.v = 0;
562
563 cp0_entry_lo0_write(lo0.value);
564 cp0_entry_lo1_write(lo1.value);
565
566 tlbwi();
567 }
568 }
569
570 interrupts_restore(ipl);
571 cp0_entry_hi_write(hi_save.value);
572}
573
574/** @}
575 */
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