source: mainline/kernel/arch/mips32/src/mm/tlb.c@ 0ff03f3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0ff03f3 was 0ff03f3, checked in by Jakub Jermar <jakub@…>, 14 years ago

Allow calling page_mapping_find() with unlocked page tables.
  • Property mode set to 100644
File size: 12.4 KB
Line 
1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32mm
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/mm/tlb.h>
36#include <mm/asid.h>
37#include <mm/tlb.h>
38#include <mm/page.h>
39#include <mm/as.h>
40#include <arch/cp0.h>
41#include <panic.h>
42#include <arch.h>
43#include <synch/mutex.h>
44#include <print.h>
45#include <debug.h>
46#include <align.h>
47#include <interrupt.h>
48#include <symtab.h>
49
50static void tlb_refill_fail(istate_t *);
51static void tlb_invalid_fail(istate_t *);
52static void tlb_modified_fail(istate_t *);
53
54static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
55
56/** Initialize TLB.
57 *
58 * Invalidate all entries and mark wired entries.
59 */
60void tlb_arch_init(void)
61{
62 int i;
63
64 cp0_pagemask_write(TLB_PAGE_MASK_16K);
65 cp0_entry_hi_write(0);
66 cp0_entry_lo0_write(0);
67 cp0_entry_lo1_write(0);
68
69 /* Clear and initialize TLB. */
70
71 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
72 cp0_index_write(i);
73 tlbwi();
74 }
75
76 /*
77 * The kernel is going to make use of some wired
78 * entries (e.g. mapping kernel stacks in kseg3).
79 */
80 cp0_wired_write(TLB_WIRED);
81}
82
83/** Process TLB Refill Exception.
84 *
85 * @param istate Interrupted register context.
86 */
87void tlb_refill(istate_t *istate)
88{
89 entry_lo_t lo;
90 entry_hi_t hi;
91 asid_t asid;
92 uintptr_t badvaddr;
93 pte_t *pte;
94 int pfrc;
95
96 badvaddr = cp0_badvaddr_read();
97
98 mutex_lock(&AS->lock);
99 asid = AS->asid;
100 mutex_unlock(&AS->lock);
101
102 page_table_lock(AS, true);
103
104 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
105 if (!pte) {
106 switch (pfrc) {
107 case AS_PF_FAULT:
108 goto fail;
109 break;
110 case AS_PF_DEFER:
111 /*
112 * The page fault came during copy_from_uspace()
113 * or copy_to_uspace().
114 */
115 page_table_unlock(AS, true);
116 return;
117 default:
118 panic("Unexpected pfrc (%d).", pfrc);
119 }
120 }
121
122 /*
123 * Record access to PTE.
124 */
125 pte->a = 1;
126
127 tlb_prepare_entry_hi(&hi, asid, badvaddr);
128 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
129 pte->pfn);
130
131 /*
132 * New entry is to be inserted into TLB
133 */
134 cp0_entry_hi_write(hi.value);
135 if ((badvaddr / PAGE_SIZE) % 2 == 0) {
136 cp0_entry_lo0_write(lo.value);
137 cp0_entry_lo1_write(0);
138 }
139 else {
140 cp0_entry_lo0_write(0);
141 cp0_entry_lo1_write(lo.value);
142 }
143 cp0_pagemask_write(TLB_PAGE_MASK_16K);
144 tlbwr();
145
146 page_table_unlock(AS, true);
147 return;
148
149fail:
150 page_table_unlock(AS, true);
151 tlb_refill_fail(istate);
152}
153
154/** Process TLB Invalid Exception.
155 *
156 * @param istate Interrupted register context.
157 */
158void tlb_invalid(istate_t *istate)
159{
160 tlb_index_t index;
161 uintptr_t badvaddr;
162 entry_lo_t lo;
163 entry_hi_t hi;
164 pte_t *pte;
165 int pfrc;
166
167 badvaddr = cp0_badvaddr_read();
168
169 /*
170 * Locate the faulting entry in TLB.
171 */
172 hi.value = cp0_entry_hi_read();
173 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
174 cp0_entry_hi_write(hi.value);
175 tlbp();
176 index.value = cp0_index_read();
177
178 page_table_lock(AS, true);
179
180 /*
181 * Fail if the entry is not in TLB.
182 */
183 if (index.p) {
184 printf("TLB entry not found.\n");
185 goto fail;
186 }
187
188 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
189 if (!pte) {
190 switch (pfrc) {
191 case AS_PF_FAULT:
192 goto fail;
193 break;
194 case AS_PF_DEFER:
195 /*
196 * The page fault came during copy_from_uspace()
197 * or copy_to_uspace().
198 */
199 page_table_unlock(AS, true);
200 return;
201 default:
202 panic("Unexpected pfrc (%d).", pfrc);
203 }
204 }
205
206 /*
207 * Read the faulting TLB entry.
208 */
209 tlbr();
210
211 /*
212 * Record access to PTE.
213 */
214 pte->a = 1;
215
216 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
217 pte->pfn);
218
219 /*
220 * The entry is to be updated in TLB.
221 */
222 if ((badvaddr / PAGE_SIZE) % 2 == 0)
223 cp0_entry_lo0_write(lo.value);
224 else
225 cp0_entry_lo1_write(lo.value);
226 cp0_pagemask_write(TLB_PAGE_MASK_16K);
227 tlbwi();
228
229 page_table_unlock(AS, true);
230 return;
231
232fail:
233 page_table_unlock(AS, true);
234 tlb_invalid_fail(istate);
235}
236
237/** Process TLB Modified Exception.
238 *
239 * @param istate Interrupted register context.
240 */
241void tlb_modified(istate_t *istate)
242{
243 tlb_index_t index;
244 uintptr_t badvaddr;
245 entry_lo_t lo;
246 entry_hi_t hi;
247 pte_t *pte;
248 int pfrc;
249
250 badvaddr = cp0_badvaddr_read();
251
252 /*
253 * Locate the faulting entry in TLB.
254 */
255 hi.value = cp0_entry_hi_read();
256 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
257 cp0_entry_hi_write(hi.value);
258 tlbp();
259 index.value = cp0_index_read();
260
261 page_table_lock(AS, true);
262
263 /*
264 * Fail if the entry is not in TLB.
265 */
266 if (index.p) {
267 printf("TLB entry not found.\n");
268 goto fail;
269 }
270
271 pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
272 if (!pte) {
273 switch (pfrc) {
274 case AS_PF_FAULT:
275 goto fail;
276 break;
277 case AS_PF_DEFER:
278 /*
279 * The page fault came during copy_from_uspace()
280 * or copy_to_uspace().
281 */
282 page_table_unlock(AS, true);
283 return;
284 default:
285 panic("Unexpected pfrc (%d).", pfrc);
286 }
287 }
288
289 /*
290 * Read the faulting TLB entry.
291 */
292 tlbr();
293
294 /*
295 * Record access and write to PTE.
296 */
297 pte->a = 1;
298 pte->d = 1;
299
300 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
301 pte->pfn);
302
303 /*
304 * The entry is to be updated in TLB.
305 */
306 if ((badvaddr / PAGE_SIZE) % 2 == 0)
307 cp0_entry_lo0_write(lo.value);
308 else
309 cp0_entry_lo1_write(lo.value);
310 cp0_pagemask_write(TLB_PAGE_MASK_16K);
311 tlbwi();
312
313 page_table_unlock(AS, true);
314 return;
315
316fail:
317 page_table_unlock(AS, true);
318 tlb_modified_fail(istate);
319}
320
321void tlb_refill_fail(istate_t *istate)
322{
323 uintptr_t va = cp0_badvaddr_read();
324
325 fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
326 (void *) va);
327 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception.");
328}
329
330
331void tlb_invalid_fail(istate_t *istate)
332{
333 uintptr_t va = cp0_badvaddr_read();
334
335 fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
336 (void *) va);
337 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception.");
338}
339
340void tlb_modified_fail(istate_t *istate)
341{
342 uintptr_t va = cp0_badvaddr_read();
343
344 fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
345 (void *) va);
346 panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception.");
347}
348
349/** Try to find PTE for faulting address.
350 *
351 * @param badvaddr Faulting virtual address.
352 * @param access Access mode that caused the fault.
353 * @param istate Pointer to interrupted state.
354 * @param pfrc Pointer to variable where as_page_fault() return code
355 * will be stored.
356 *
357 * @return PTE on success, NULL otherwise.
358 */
359pte_t *
360find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
361 int *pfrc)
362{
363 entry_hi_t hi;
364 pte_t *pte;
365
366 ASSERT(mutex_locked(&AS->lock));
367
368 hi.value = cp0_entry_hi_read();
369
370 /*
371 * Handler cannot succeed if the ASIDs don't match.
372 */
373 if (hi.asid != AS->asid) {
374 printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
375 return NULL;
376 }
377
378 /*
379 * Check if the mapping exists in page tables.
380 */
381 pte = page_mapping_find(AS, badvaddr, true);
382 if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
383 /*
384 * Mapping found in page tables.
385 * Immediately succeed.
386 */
387 return pte;
388 } else {
389 int rc;
390
391 /*
392 * Mapping not found in page tables.
393 * Resort to higher-level page fault handler.
394 */
395 page_table_unlock(AS, true);
396 switch (rc = as_page_fault(badvaddr, access, istate)) {
397 case AS_PF_OK:
398 /*
399 * The higher-level page fault handler succeeded,
400 * The mapping ought to be in place.
401 */
402 page_table_lock(AS, true);
403 pte = page_mapping_find(AS, badvaddr, true);
404 ASSERT(pte && pte->p);
405 ASSERT(pte->w || access != PF_ACCESS_WRITE);
406 return pte;
407 break;
408 case AS_PF_DEFER:
409 page_table_lock(AS, true);
410 *pfrc = AS_PF_DEFER;
411 return NULL;
412 break;
413 case AS_PF_FAULT:
414 page_table_lock(AS, true);
415 *pfrc = AS_PF_FAULT;
416 return NULL;
417 break;
418 default:
419 panic("Unexpected rc (%d).", rc);
420 }
421
422 }
423}
424
425void
426tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
427 uintptr_t pfn)
428{
429 lo->value = 0;
430 lo->g = g;
431 lo->v = v;
432 lo->d = d;
433 lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
434 lo->pfn = pfn;
435}
436
437void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
438{
439 hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
440 hi->asid = asid;
441}
442
443/** Print contents of TLB. */
444void tlb_print(void)
445{
446 page_mask_t mask;
447 entry_lo_t lo0, lo1;
448 entry_hi_t hi, hi_save;
449 unsigned int i;
450
451 hi_save.value = cp0_entry_hi_read();
452
453 printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n");
454
455 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
456 cp0_index_write(i);
457 tlbr();
458
459 mask.value = cp0_pagemask_read();
460 hi.value = cp0_entry_hi_read();
461 lo0.value = cp0_entry_lo0_read();
462 lo1.value = cp0_entry_lo1_read();
463
464 printf("%-4u %-6u %#6x %#6x %1u%1u%1u%1u %#6x\n",
465 i, hi.asid, hi.vpn2, mask.mask,
466 lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
467 printf(" %1u%1u%1u%1u %#6x\n",
468 lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
469 }
470
471 cp0_entry_hi_write(hi_save.value);
472}
473
474/** Invalidate all not wired TLB entries. */
475void tlb_invalidate_all(void)
476{
477 ipl_t ipl;
478 entry_lo_t lo0, lo1;
479 entry_hi_t hi_save;
480 int i;
481
482 hi_save.value = cp0_entry_hi_read();
483 ipl = interrupts_disable();
484
485 for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
486 cp0_index_write(i);
487 tlbr();
488
489 lo0.value = cp0_entry_lo0_read();
490 lo1.value = cp0_entry_lo1_read();
491
492 lo0.v = 0;
493 lo1.v = 0;
494
495 cp0_entry_lo0_write(lo0.value);
496 cp0_entry_lo1_write(lo1.value);
497
498 tlbwi();
499 }
500
501 interrupts_restore(ipl);
502 cp0_entry_hi_write(hi_save.value);
503}
504
505/** Invalidate all TLB entries belonging to specified address space.
506 *
507 * @param asid Address space identifier.
508 */
509void tlb_invalidate_asid(asid_t asid)
510{
511 ipl_t ipl;
512 entry_lo_t lo0, lo1;
513 entry_hi_t hi, hi_save;
514 int i;
515
516 ASSERT(asid != ASID_INVALID);
517
518 hi_save.value = cp0_entry_hi_read();
519 ipl = interrupts_disable();
520
521 for (i = 0; i < TLB_ENTRY_COUNT; i++) {
522 cp0_index_write(i);
523 tlbr();
524
525 hi.value = cp0_entry_hi_read();
526
527 if (hi.asid == asid) {
528 lo0.value = cp0_entry_lo0_read();
529 lo1.value = cp0_entry_lo1_read();
530
531 lo0.v = 0;
532 lo1.v = 0;
533
534 cp0_entry_lo0_write(lo0.value);
535 cp0_entry_lo1_write(lo1.value);
536
537 tlbwi();
538 }
539 }
540
541 interrupts_restore(ipl);
542 cp0_entry_hi_write(hi_save.value);
543}
544
545/** Invalidate TLB entries for specified page range belonging to specified
546 * address space.
547 *
548 * @param asid Address space identifier.
549 * @param page First page whose TLB entry is to be invalidated.
550 * @param cnt Number of entries to invalidate.
551 */
552void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
553{
554 unsigned int i;
555 ipl_t ipl;
556 entry_lo_t lo0, lo1;
557 entry_hi_t hi, hi_save;
558 tlb_index_t index;
559
560 if (asid == ASID_INVALID)
561 return;
562
563 hi_save.value = cp0_entry_hi_read();
564 ipl = interrupts_disable();
565
566 for (i = 0; i < cnt + 1; i += 2) {
567 hi.value = 0;
568 tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
569 cp0_entry_hi_write(hi.value);
570
571 tlbp();
572 index.value = cp0_index_read();
573
574 if (!index.p) {
575 /*
576 * Entry was found, index register contains valid
577 * index.
578 */
579 tlbr();
580
581 lo0.value = cp0_entry_lo0_read();
582 lo1.value = cp0_entry_lo1_read();
583
584 lo0.v = 0;
585 lo1.v = 0;
586
587 cp0_entry_lo0_write(lo0.value);
588 cp0_entry_lo1_write(lo1.value);
589
590 tlbwi();
591 }
592 }
593
594 interrupts_restore(ipl);
595 cp0_entry_hi_write(hi_save.value);
596}
597
598/** @}
599 */
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