source: mainline/kernel/arch/mips32/src/mips32.c@ ff685c9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ff685c9 was 06f96234, checked in by Jiri Svoboda <jirik.svoboda@…>, 16 years ago

Unify arch_pre_main() comments.

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <arch/cp0.h>
37#include <arch/exception.h>
38#include <mm/as.h>
39
40#include <userspace.h>
41#include <arch/console.h>
42#include <memstr.h>
43#include <proc/thread.h>
44#include <proc/uarg.h>
45#include <print.h>
46#include <syscall/syscall.h>
47#include <sysinfo/sysinfo.h>
48
49#include <arch/interrupt.h>
50#include <console/chardev.h>
51#include <arch/barrier.h>
52#include <arch/debugger.h>
53#include <genarch/fb/fb.h>
54#include <genarch/fb/visuals.h>
55#include <macros.h>
56#include <ddi/device.h>
57
58#include <arch/asm/regname.h>
59
60/* Size of the code jumping to the exception handler code
61 * - J+NOP
62 */
63#define EXCEPTION_JUMP_SIZE 8
64
65#define TLB_EXC ((char *) 0x80000000)
66#define NORM_EXC ((char *) 0x80000180)
67#define CACHE_EXC ((char *) 0x80000100)
68
69
70/* Why the linker moves the variable 64K away in assembler
71 * when not in .text section?
72 */
73
74/* Stack pointer saved when entering user mode */
75uintptr_t supervisor_sp __attribute__ ((section (".text")));
76
77count_t cpu_count = 0;
78
79/** Performs mips32-specific initialization before main_bsp() is called. */
80void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
81{
82 /* Setup usermode */
83 init.cnt = bootinfo->cnt;
84
85 count_t i;
86 for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {
87 init.tasks[i].addr = bootinfo->tasks[i].addr;
88 init.tasks[i].size = bootinfo->tasks[i].size;
89 }
90
91 for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
92 if ((bootinfo->cpumap & (1 << i)) != 0)
93 cpu_count++;
94 }
95}
96
97void arch_pre_mm_init(void)
98{
99 /* It is not assumed by default */
100 interrupts_disable();
101
102 /* Initialize dispatch table */
103 exception_init();
104
105 /* Copy the exception vectors to the right places */
106 memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
107 smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
108 memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
109 smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
110 memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
111 smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
112
113 /*
114 * Switch to BEV normal level so that exception vectors point to the
115 * kernel. Clear the error level.
116 */
117 cp0_status_write(cp0_status_read() &
118 ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
119
120 /*
121 * Mask all interrupts
122 */
123 cp0_mask_all_int();
124
125 debugger_init();
126}
127
128void arch_post_mm_init(void)
129{
130 interrupt_init();
131 console_init(device_assign_devno());
132#ifdef CONFIG_FB
133 /* GXemul framebuffer */
134 fb_properties_t gxemul_prop = {
135 .addr = 0x12000000,
136 .offset = 0,
137 .x = 640,
138 .y = 480,
139 .scan = 1920,
140 .visual = VISUAL_BGR_8_8_8,
141 };
142 fb_init(&gxemul_prop);
143#endif
144
145#ifdef MACHINE_msim
146 sysinfo_set_item_val("machine.msim", NULL, 1);
147#endif
148
149#ifdef MACHINE_simics
150 sysinfo_set_item_val("machine.simics", NULL, 1);
151#endif
152
153#ifdef MACHINE_bgxemul
154 sysinfo_set_item_val("machine.bgxemul", NULL, 1);
155#endif
156
157#ifdef MACHINE_lgxemul
158 sysinfo_set_item_val("machine.lgxemul", NULL, 1);
159#endif
160}
161
162void arch_post_cpu_init(void)
163{
164}
165
166void arch_pre_smp_init(void)
167{
168}
169
170void arch_post_smp_init(void)
171{
172}
173
174void calibrate_delay_loop(void)
175{
176}
177
178void userspace(uspace_arg_t *kernel_uarg)
179{
180 /* EXL = 1, UM = 1, IE = 1 */
181 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
182 cp0_status_um_bit | cp0_status_ie_enabled_bit));
183 cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
184 userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),
185 (uintptr_t) kernel_uarg->uspace_uarg,
186 (uintptr_t) kernel_uarg->uspace_entry);
187
188 while (1);
189}
190
191/** Perform mips32 specific tasks needed before the new task is run. */
192void before_task_runs_arch(void)
193{
194}
195
196/** Perform mips32 specific tasks needed before the new thread is scheduled. */
197void before_thread_runs_arch(void)
198{
199 supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
200 SP_DELTA];
201}
202
203void after_thread_ran_arch(void)
204{
205}
206
207/** Set thread-local-storage pointer
208 *
209 * We have it currently in K1, it is
210 * possible to have it separately in the future.
211 */
212unative_t sys_tls_set(unative_t addr)
213{
214 return 0;
215}
216
217void arch_reboot(void)
218{
219 ___halt();
220
221 while (1);
222}
223
224/** Construct function pointer
225 *
226 * @param fptr function pointer structure
227 * @param addr function address
228 * @param caller calling function address
229 *
230 * @return address of the function pointer
231 *
232 */
233void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
234{
235 return addr;
236}
237
238/** @}
239 */
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