source: mainline/kernel/arch/mips32/src/mips32.c@ 534bcdf

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 534bcdf was 63a045c, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 7 years ago

Unify handling of compressed init data and use regular tar + gzip to achieve it

There are two issues this commit solves.

First is that architecture-specific code duplicates most of the init binary
handling in each architecture, each with miniscule and confusing variations.
After this commit, the init binary expansion is almost entirely handled by
unified generic code.

Second is that the way we used to generate the incorporated data is somewhat
convoluted. Previously we have a Python script which generates a zip archive
with individual deflate-compressed files and accompanying header and C files
which contain structures describing the archive contents.
The zip file is then extracted and the individual deflate-compressed files are
included in the binary via assembler code.
Since gas doesn't take particular care to be consistent between architectures,
the assembly portions are also not uniform and the build script needs to know
particulars of the architecture's assembly.

Instead of doing that, after this commit we first gzip each included file, then
we pack the gzipped files into a tar archive, and then we include the archive
into the binary using objcopy.
Linker script provides symbols for the start and end of the archive,
and the payload is in a self-describing format, so there is no need for any
generated code.

Note that we are doing the opposite of the conventional .tar.gz format.
It would be somewhat inconvenient to use .tar.gz since the uncompressed files
need to be aligned to page size, so we'd have to first decompress the entire
payload to determine the final position of the files (and hence the required
amount of memory).

  • Property mode set to 100644
File size: 5.7 KB
Line 
1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_mips32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <arch/arch.h>
37#include <typedefs.h>
38#include <errno.h>
39#include <interrupt.h>
40#include <macros.h>
41#include <str.h>
42#include <mem.h>
43#include <userspace.h>
44#include <stdbool.h>
45#include <syscall/syscall.h>
46#include <sysinfo/sysinfo.h>
47#include <arch/debug.h>
48#include <arch/debugger.h>
49#include <arch/machine_func.h>
50
51/*
52 * Size of the code jumping to the exception handler code
53 * - J+NOP
54 */
55#define EXCEPTION_JUMP_SIZE 8
56
57#define TLB_EXC ((char *) 0x80000000)
58#define NORM_EXC ((char *) 0x80000180)
59#define CACHE_EXC ((char *) 0x80000100)
60
61static void mips32_pre_mm_init(void);
62static void mips32_post_mm_init(void);
63static void mips32_post_smp_init(void);
64
65arch_ops_t mips32_ops = {
66 .pre_mm_init = mips32_pre_mm_init,
67 .post_mm_init = mips32_post_mm_init,
68 .post_smp_init = mips32_post_smp_init,
69};
70
71arch_ops_t *arch_ops = &mips32_ops;
72
73/*
74 * Why the linker moves the variable 64K away in assembler
75 * when not in .text section?
76 */
77
78/* Stack pointer saved when entering user mode */
79uintptr_t supervisor_sp __attribute__((section(".text")));
80
81size_t cpu_count = 0;
82
83#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
84size_t sdram_size = 0;
85#endif
86
87/** Performs mips32-specific initialization before main_bsp() is called. */
88void mips32_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
89{
90 init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
91
92 size_t i;
93 for (i = 0; i < init.cnt; i++) {
94 init.tasks[i].paddr = KA2PA(bootinfo->taskmap.tasks[i].addr);
95 init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
96 str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
97 bootinfo->taskmap.tasks[i].name);
98 }
99
100 for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
101 if ((bootinfo->cpumap & (1 << i)) != 0)
102 cpu_count++;
103 }
104
105#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
106 sdram_size = bootinfo->sdram_size;
107#endif
108
109 /* Initialize machine_ops pointer. */
110 machine_ops_init();
111}
112
113void mips32_pre_mm_init(void)
114{
115 /* It is not assumed by default */
116 interrupts_disable();
117
118 /* Initialize dispatch table */
119 exception_init();
120
121 /* Copy the exception vectors to the right places */
122 memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
123 smc_coherence(TLB_EXC, EXCEPTION_JUMP_SIZE);
124 memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
125 smc_coherence(NORM_EXC, EXCEPTION_JUMP_SIZE);
126 memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
127 smc_coherence(CACHE_EXC, EXCEPTION_JUMP_SIZE);
128
129 /*
130 * Switch to BEV normal level so that exception vectors point to the
131 * kernel. Clear the error level.
132 */
133 cp0_status_write(cp0_status_read() &
134 ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
135
136 /*
137 * Mask all interrupts
138 */
139 cp0_mask_all_int();
140
141 debugger_init();
142}
143
144void mips32_post_mm_init(void)
145{
146 interrupt_init();
147
148 machine_init();
149 machine_output_init();
150}
151
152void mips32_post_smp_init(void)
153{
154 /* Set platform name. */
155 sysinfo_set_item_data("platform", NULL,
156 (void *) machine_get_platform_name(),
157 str_size(machine_get_platform_name()));
158
159 machine_input_init();
160}
161
162void calibrate_delay_loop(void)
163{
164}
165
166void userspace(uspace_arg_t *kernel_uarg)
167{
168 /* EXL = 1, UM = 1, IE = 1 */
169 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
170 cp0_status_um_bit | cp0_status_ie_enabled_bit));
171 cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
172 userspace_asm(((uintptr_t) kernel_uarg->uspace_stack +
173 kernel_uarg->uspace_stack_size),
174 (uintptr_t) kernel_uarg->uspace_uarg,
175 (uintptr_t) kernel_uarg->uspace_entry);
176
177 while (true)
178 ;
179}
180
181/** Perform mips32 specific tasks needed before the new task is run. */
182void before_task_runs_arch(void)
183{
184}
185
186/** Perform mips32 specific tasks needed before the new thread is scheduled. */
187void before_thread_runs_arch(void)
188{
189 supervisor_sp =
190 (uintptr_t) &THREAD->kstack[STACK_SIZE];
191}
192
193void after_thread_ran_arch(void)
194{
195}
196
197void arch_reboot(void)
198{
199 ___halt();
200 while (true)
201 ;
202}
203
204/** Construct function pointer
205 *
206 * @param fptr function pointer structure
207 * @param addr function address
208 * @param caller calling function address
209 *
210 * @return address of the function pointer
211 *
212 */
213void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
214{
215 return addr;
216}
217
218void irq_initialize_arch(irq_t *irq)
219{
220 (void) irq;
221}
222
223/** @}
224 */
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