source: mainline/kernel/arch/mips32/src/mips32.c@ c5429fe

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c5429fe was c5429fe, checked in by Jakub Jermar <jakub@…>, 7 years ago

Disambiguate architecture specific doxygroups

  • Property mode set to 100644
File size: 5.7 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[c5429fe]29/** @addtogroup kernel_mips32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch.h>
[36df4109]36#include <arch/arch.h>
[d8db519]37#include <typedefs.h>
38#include <errno.h>
39#include <interrupt.h>
40#include <macros.h>
41#include <str.h>
[44a7ee5]42#include <mem.h>
[d8db519]43#include <userspace.h>
[76d0981d]44#include <stdbool.h>
[281b607]45#include <syscall/syscall.h>
[06a583e]46#include <sysinfo/sysinfo.h>
[d8db519]47#include <arch/debug.h>
[5bb8e45]48#include <arch/debugger.h>
[ae7ba7b6]49#include <arch/machine_func.h>
[973be64e]50
[7c3fb9b]51/*
52 * Size of the code jumping to the exception handler code
[96e0748d]53 * - J+NOP
[ffc277e]54 */
[96e0748d]55#define EXCEPTION_JUMP_SIZE 8
[ffc277e]56
[96e0748d]57#define TLB_EXC ((char *) 0x80000000)
58#define NORM_EXC ((char *) 0x80000180)
59#define CACHE_EXC ((char *) 0x80000100)
[ffc277e]60
[36df4109]61static void mips32_pre_mm_init(void);
62static void mips32_post_mm_init(void);
63static void mips32_post_smp_init(void);
64
65arch_ops_t mips32_ops = {
66 .pre_mm_init = mips32_pre_mm_init,
67 .post_mm_init = mips32_post_mm_init,
68 .post_smp_init = mips32_post_smp_init,
69};
70
71arch_ops_t *arch_ops = &mips32_ops;
[8449000]72
[7c3fb9b]73/*
74 * Why the linker moves the variable 64K away in assembler
[96e0748d]75 * when not in .text section?
[8449000]76 */
[96e0748d]77
[8449000]78/* Stack pointer saved when entering user mode */
[1433ecda]79uintptr_t supervisor_sp __attribute__((section(".text")));
[971cf31f]80
[98000fb]81size_t cpu_count = 0;
[96e0748d]82
[bcad855]83#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
84size_t sdram_size = 0;
85#endif
86
[06f96234]87/** Performs mips32-specific initialization before main_bsp() is called. */
[36df4109]88void mips32_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
[12c7f27]89{
[4872160]90 init.cnt = min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
[a35b458]91
[98000fb]92 size_t i;
[4872160]93 for (i = 0; i < init.cnt; i++) {
[32817cc]94 init.tasks[i].paddr = KA2PA(bootinfo->tasks[i].addr);
[96e0748d]95 init.tasks[i].size = bootinfo->tasks[i].size;
[f4b1535]96 str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
97 bootinfo->tasks[i].name);
[96e0748d]98 }
[a35b458]99
[96e0748d]100 for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
101 if ((bootinfo->cpumap & (1 << i)) != 0)
102 cpu_count++;
[971cf31f]103 }
[bcad855]104
105#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
106 sdram_size = bootinfo->sdram_size;
107#endif
[260f678]108
109 /* Initialize machine_ops pointer. */
110 machine_ops_init();
[12c7f27]111}
112
[36df4109]113void mips32_pre_mm_init(void)
[f761f1eb]114{
[24241cf]115 /* It is not assumed by default */
[22f7769]116 interrupts_disable();
[a35b458]117
[973be64e]118 /* Initialize dispatch table */
[7a8c866a]119 exception_init();
[3156582]120
[ffc277e]121 /* Copy the exception vectors to the right places */
[7688b5d]122 memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
[0abc2ae]123 smc_coherence(TLB_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]124 memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
[0abc2ae]125 smc_coherence(NORM_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]126 memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
[0abc2ae]127 smc_coherence(CACHE_EXC, EXCEPTION_JUMP_SIZE);
[a35b458]128
[f761f1eb]129 /*
[c7511ec]130 * Switch to BEV normal level so that exception vectors point to the
131 * kernel. Clear the error level.
[f761f1eb]132 */
[c7511ec]133 cp0_status_write(cp0_status_read() &
134 ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
[a35b458]135
[6da1013f]136 /*
137 * Mask all interrupts
[24241cf]138 */
139 cp0_mask_all_int();
[a35b458]140
[5bb8e45]141 debugger_init();
[f761f1eb]142}
[7eade45]143
[36df4109]144void mips32_post_mm_init(void)
[7eade45]145{
[7688b5d]146 interrupt_init();
[260f678]147
148 machine_init();
149 machine_output_init();
[7eade45]150}
[babcb148]151
[36df4109]152void mips32_post_smp_init(void)
[babcb148]153{
[eff1f033]154 /* Set platform name. */
[ae7ba7b6]155 sysinfo_set_item_data("platform", NULL,
156 (void *) machine_get_platform_name(),
157 str_size(machine_get_platform_name()));
[eff1f033]158
[260f678]159 machine_input_init();
[babcb148]160}
[2bd4fdf]161
[7f341820]162void calibrate_delay_loop(void)
163{
164}
165
[0f250f9]166void userspace(uspace_arg_t *kernel_uarg)
[2bd4fdf]167{
[b5ed4f8]168 /* EXL = 1, UM = 1, IE = 1 */
[2bd4fdf]169 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
[c7511ec]170 cp0_status_um_bit | cp0_status_ie_enabled_bit));
[7f1c620]171 cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
[2902e1bb]172 userspace_asm(((uintptr_t) kernel_uarg->uspace_stack +
173 kernel_uarg->uspace_stack_size),
[c7511ec]174 (uintptr_t) kernel_uarg->uspace_uarg,
175 (uintptr_t) kernel_uarg->uspace_entry);
[a35b458]176
[76d0981d]177 while (true)
[1433ecda]178 ;
[2bd4fdf]179}
180
[39cea6a]181/** Perform mips32 specific tasks needed before the new task is run. */
182void before_task_runs_arch(void)
183{
184}
185
186/** Perform mips32 specific tasks needed before the new thread is scheduled. */
[2bd4fdf]187void before_thread_runs_arch(void)
188{
[26aafe8]189 supervisor_sp =
[2277e03]190 (uintptr_t) &THREAD->kstack[STACK_SIZE];
[2bd4fdf]191}
[97f1691]192
193void after_thread_ran_arch(void)
194{
195}
[281b607]196
[f74bbaf]197void arch_reboot(void)
198{
[edebc15c]199 ___halt();
[76d0981d]200 while (true)
[1433ecda]201 ;
[6da1013f]202}
203
204/** Construct function pointer
205 *
206 * @param fptr function pointer structure
207 * @param addr function address
208 * @param caller calling function address
209 *
210 * @return address of the function pointer
211 *
212 */
213void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
214{
215 return addr;
[f74bbaf]216}
217
[3a2f8aa]218void irq_initialize_arch(irq_t *irq)
219{
220 (void) irq;
221}
222
[d227101]223/** @}
[b45c443]224 */
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