source: mainline/kernel/arch/mips32/src/mips32.c@ 81c8d54

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 81c8d54 was 7f341820, checked in by Martin Decky <martin@…>, 17 years ago

mips32: basic SMP support

  • Property mode set to 100644
File size: 5.7 KB
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[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[d227101]29/** @addtogroup mips32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch.h>
[971cf31f]36#include <arch/boot.h>
[f761f1eb]37#include <arch/cp0.h>
38#include <arch/exception.h>
[20d50a1]39#include <mm/as.h>
[973be64e]40
[2bd4fdf]41#include <userspace.h>
[38de8a5]42#include <arch/console.h>
[ffc277e]43#include <memstr.h>
[1084a784]44#include <proc/thread.h>
[0f250f9]45#include <proc/uarg.h>
[a1493d9]46#include <print.h>
[281b607]47#include <syscall/syscall.h>
[06a583e]48#include <sysinfo/sysinfo.h>
[a1493d9]49
[973be64e]50#include <arch/interrupt.h>
51#include <console/chardev.h>
[c7511ec]52#include <arch/barrier.h>
[5bb8e45]53#include <arch/debugger.h>
[bd55bbb]54#include <genarch/fb/fb.h>
[2bc137c2]55#include <genarch/fb/visuals.h>
[d227101]56#include <macros.h>
[7688b5d]57#include <ddi/device.h>
[973be64e]58
59#include <arch/asm/regname.h>
60
[ffc277e]61/* Size of the code jumping to the exception handler code
62 * - J+NOP
63 */
64#define EXCEPTION_JUMP_SIZE 8
65
66#define TLB_EXC ((char *) 0x80000000)
67#define NORM_EXC ((char *) 0x80000180)
68#define CACHE_EXC ((char *) 0x80000100)
69
[8449000]70
71/* Why the linker moves the variable 64K away in assembler
72 * when not in .text section ????????
73 */
[7f1c620]74uintptr_t supervisor_sp __attribute__ ((section (".text")));
[8449000]75/* Stack pointer saved when entering user mode */
76/* TODO: How do we do it on SMP system???? */
77bootinfo_t bootinfo __attribute__ ((section (".text")));
[971cf31f]78
[12c7f27]79void arch_pre_main(void)
80{
81 /* Setup usermode */
[971cf31f]82 init.cnt = bootinfo.cnt;
83
[7f1c620]84 uint32_t i;
[971cf31f]85
86 for (i = 0; i < bootinfo.cnt; i++) {
87 init.tasks[i].addr = bootinfo.tasks[i].addr;
88 init.tasks[i].size = bootinfo.tasks[i].size;
89 }
[12c7f27]90}
91
[f07bba5]92void arch_pre_mm_init(void)
[f761f1eb]93{
[24241cf]94 /* It is not assumed by default */
[22f7769]95 interrupts_disable();
[973be64e]96
97 /* Initialize dispatch table */
[7a8c866a]98 exception_init();
[3156582]99
[ffc277e]100 /* Copy the exception vectors to the right places */
[7688b5d]101 memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
[c7511ec]102 smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]103 memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
[c7511ec]104 smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]105 memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
[c7511ec]106 smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]107
[f761f1eb]108 /*
[c7511ec]109 * Switch to BEV normal level so that exception vectors point to the
110 * kernel. Clear the error level.
[f761f1eb]111 */
[c7511ec]112 cp0_status_write(cp0_status_read() &
113 ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
[6da1013f]114
115 /*
116 * Mask all interrupts
[24241cf]117 */
118 cp0_mask_all_int();
[6da1013f]119
[5bb8e45]120 debugger_init();
[f761f1eb]121}
[7eade45]122
123void arch_post_mm_init(void)
124{
[7688b5d]125 interrupt_init();
126 console_init(device_assign_devno());
[bd55bbb]127#ifdef CONFIG_FB
[c7511ec]128 /* GXemul framebuffer */
[965dc18]129 fb_properties_t gxemul_prop = {
130 .addr = 0x12000000,
131 .offset = 0,
132 .x = 640,
133 .y = 480,
134 .scan = 1920,
[6da1013f]135 .visual = VISUAL_BGR_8_8_8,
[965dc18]136 };
137 fb_init(&gxemul_prop);
[bd55bbb]138#endif
[6da1013f]139
[e94f730]140#ifdef MACHINE_msim
[6da1013f]141 sysinfo_set_item_val("machine.msim", NULL, 1);
142#endif
143
[e94f730]144#ifdef MACHINE_simics
[6da1013f]145 sysinfo_set_item_val("machine.simics", NULL, 1);
146#endif
147
[e94f730]148#ifdef MACHINE_bgxemul
[6da1013f]149 sysinfo_set_item_val("machine.bgxemul", NULL, 1);
150#endif
151
[e94f730]152#ifdef MACHINE_lgxemul
[6da1013f]153 sysinfo_set_item_val("machine.lgxemul", NULL, 1);
154#endif
[7eade45]155}
[babcb148]156
[26678e5]157void arch_post_cpu_init(void)
158{
159}
160
[7453929]161void arch_pre_smp_init(void)
162{
163}
164
165void arch_post_smp_init(void)
[babcb148]166{
167}
[2bd4fdf]168
[7f341820]169void calibrate_delay_loop(void)
170{
171}
172
[0f250f9]173void userspace(uspace_arg_t *kernel_uarg)
[2bd4fdf]174{
[b5ed4f8]175 /* EXL = 1, UM = 1, IE = 1 */
[2bd4fdf]176 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
[c7511ec]177 cp0_status_um_bit | cp0_status_ie_enabled_bit));
[7f1c620]178 cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
[b5ed4f8]179 userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),
[c7511ec]180 (uintptr_t) kernel_uarg->uspace_uarg,
181 (uintptr_t) kernel_uarg->uspace_entry);
[b5ed4f8]182
[6da1013f]183 while (1);
[2bd4fdf]184}
185
[39cea6a]186/** Perform mips32 specific tasks needed before the new task is run. */
187void before_task_runs_arch(void)
188{
189}
190
191/** Perform mips32 specific tasks needed before the new thread is scheduled. */
[2bd4fdf]192void before_thread_runs_arch(void)
193{
[c7511ec]194 supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
195 SP_DELTA];
[2bd4fdf]196}
[97f1691]197
198void after_thread_ran_arch(void)
199{
200}
[281b607]201
[e1be3b6]202/** Set thread-local-storage pointer
[281b607]203 *
204 * We have it currently in K1, it is
205 * possible to have it separately in the future.
206 */
[7f1c620]207unative_t sys_tls_set(unative_t addr)
[281b607]208{
209 return 0;
210}
[41d33ac]211
[f74bbaf]212void arch_reboot(void)
213{
[edebc15c]214 ___halt();
[b5ed4f8]215
[6da1013f]216 while (1);
217}
218
219/** Construct function pointer
220 *
221 * @param fptr function pointer structure
222 * @param addr function address
223 * @param caller calling function address
224 *
225 * @return address of the function pointer
226 *
227 */
228void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
229{
230 return addr;
[f74bbaf]231}
232
[d227101]233/** @}
[b45c443]234 */
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