source: mainline/kernel/arch/mips32/src/mips32.c@ 430afff

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 430afff was 96e0748d, checked in by Martin Decky <martin@…>, 17 years ago

make arch_pre_main optional, don't force any specific prototype
simplify boot process
mips32: detect number of configured CPUs in msim

  • Property mode set to 100644
File size: 5.8 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[d227101]29/** @addtogroup mips32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch.h>
36#include <arch/cp0.h>
37#include <arch/exception.h>
[20d50a1]38#include <mm/as.h>
[973be64e]39
[2bd4fdf]40#include <userspace.h>
[38de8a5]41#include <arch/console.h>
[ffc277e]42#include <memstr.h>
[1084a784]43#include <proc/thread.h>
[0f250f9]44#include <proc/uarg.h>
[a1493d9]45#include <print.h>
[281b607]46#include <syscall/syscall.h>
[06a583e]47#include <sysinfo/sysinfo.h>
[a1493d9]48
[973be64e]49#include <arch/interrupt.h>
50#include <console/chardev.h>
[c7511ec]51#include <arch/barrier.h>
[5bb8e45]52#include <arch/debugger.h>
[bd55bbb]53#include <genarch/fb/fb.h>
[2bc137c2]54#include <genarch/fb/visuals.h>
[d227101]55#include <macros.h>
[7688b5d]56#include <ddi/device.h>
[973be64e]57
58#include <arch/asm/regname.h>
59
[96e0748d]60/* Size of the code jumping to the exception handler code
61 * - J+NOP
[ffc277e]62 */
[96e0748d]63#define EXCEPTION_JUMP_SIZE 8
[ffc277e]64
[96e0748d]65#define TLB_EXC ((char *) 0x80000000)
66#define NORM_EXC ((char *) 0x80000180)
67#define CACHE_EXC ((char *) 0x80000100)
[ffc277e]68
[8449000]69
70/* Why the linker moves the variable 64K away in assembler
[96e0748d]71 * when not in .text section?
[8449000]72 */
[96e0748d]73
[8449000]74/* Stack pointer saved when entering user mode */
[96e0748d]75uintptr_t supervisor_sp __attribute__ ((section (".text")));
[971cf31f]76
[96e0748d]77count_t cpu_count = 0;
78
79void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
[12c7f27]80{
81 /* Setup usermode */
[96e0748d]82 init.cnt = bootinfo->cnt;
[971cf31f]83
[96e0748d]84 count_t i;
85 for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {
86 init.tasks[i].addr = bootinfo->tasks[i].addr;
87 init.tasks[i].size = bootinfo->tasks[i].size;
88 }
[971cf31f]89
[96e0748d]90 for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
91 if ((bootinfo->cpumap & (1 << i)) != 0)
92 cpu_count++;
[971cf31f]93 }
[12c7f27]94}
95
[f07bba5]96void arch_pre_mm_init(void)
[f761f1eb]97{
[24241cf]98 /* It is not assumed by default */
[22f7769]99 interrupts_disable();
[973be64e]100
101 /* Initialize dispatch table */
[7a8c866a]102 exception_init();
[3156582]103
[ffc277e]104 /* Copy the exception vectors to the right places */
[7688b5d]105 memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
[c7511ec]106 smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]107 memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
[c7511ec]108 smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]109 memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
[c7511ec]110 smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
[7688b5d]111
[f761f1eb]112 /*
[c7511ec]113 * Switch to BEV normal level so that exception vectors point to the
114 * kernel. Clear the error level.
[f761f1eb]115 */
[c7511ec]116 cp0_status_write(cp0_status_read() &
117 ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
[6da1013f]118
119 /*
120 * Mask all interrupts
[24241cf]121 */
122 cp0_mask_all_int();
[6da1013f]123
[5bb8e45]124 debugger_init();
[f761f1eb]125}
[7eade45]126
127void arch_post_mm_init(void)
128{
[7688b5d]129 interrupt_init();
130 console_init(device_assign_devno());
[bd55bbb]131#ifdef CONFIG_FB
[c7511ec]132 /* GXemul framebuffer */
[965dc18]133 fb_properties_t gxemul_prop = {
134 .addr = 0x12000000,
135 .offset = 0,
136 .x = 640,
137 .y = 480,
138 .scan = 1920,
[6da1013f]139 .visual = VISUAL_BGR_8_8_8,
[965dc18]140 };
141 fb_init(&gxemul_prop);
[bd55bbb]142#endif
[6da1013f]143
[e94f730]144#ifdef MACHINE_msim
[6da1013f]145 sysinfo_set_item_val("machine.msim", NULL, 1);
146#endif
147
[e94f730]148#ifdef MACHINE_simics
[6da1013f]149 sysinfo_set_item_val("machine.simics", NULL, 1);
150#endif
151
[e94f730]152#ifdef MACHINE_bgxemul
[6da1013f]153 sysinfo_set_item_val("machine.bgxemul", NULL, 1);
154#endif
155
[e94f730]156#ifdef MACHINE_lgxemul
[6da1013f]157 sysinfo_set_item_val("machine.lgxemul", NULL, 1);
158#endif
[7eade45]159}
[babcb148]160
[26678e5]161void arch_post_cpu_init(void)
162{
163}
164
[7453929]165void arch_pre_smp_init(void)
166{
167}
168
169void arch_post_smp_init(void)
[babcb148]170{
171}
[2bd4fdf]172
[7f341820]173void calibrate_delay_loop(void)
174{
175}
176
[0f250f9]177void userspace(uspace_arg_t *kernel_uarg)
[2bd4fdf]178{
[b5ed4f8]179 /* EXL = 1, UM = 1, IE = 1 */
[2bd4fdf]180 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
[c7511ec]181 cp0_status_um_bit | cp0_status_ie_enabled_bit));
[7f1c620]182 cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
[b5ed4f8]183 userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),
[c7511ec]184 (uintptr_t) kernel_uarg->uspace_uarg,
185 (uintptr_t) kernel_uarg->uspace_entry);
[b5ed4f8]186
[6da1013f]187 while (1);
[2bd4fdf]188}
189
[39cea6a]190/** Perform mips32 specific tasks needed before the new task is run. */
191void before_task_runs_arch(void)
192{
193}
194
195/** Perform mips32 specific tasks needed before the new thread is scheduled. */
[2bd4fdf]196void before_thread_runs_arch(void)
197{
[c7511ec]198 supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
199 SP_DELTA];
[2bd4fdf]200}
[97f1691]201
202void after_thread_ran_arch(void)
203{
204}
[281b607]205
[e1be3b6]206/** Set thread-local-storage pointer
[281b607]207 *
208 * We have it currently in K1, it is
209 * possible to have it separately in the future.
210 */
[7f1c620]211unative_t sys_tls_set(unative_t addr)
[281b607]212{
213 return 0;
214}
[41d33ac]215
[f74bbaf]216void arch_reboot(void)
217{
[edebc15c]218 ___halt();
[b5ed4f8]219
[6da1013f]220 while (1);
221}
222
223/** Construct function pointer
224 *
225 * @param fptr function pointer structure
226 * @param addr function address
227 * @param caller calling function address
228 *
229 * @return address of the function pointer
230 *
231 */
232void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
233{
234 return addr;
[f74bbaf]235}
236
[d227101]237/** @}
[b45c443]238 */
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