[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2003-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_mips32
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[f761f1eb] | 35 | #include <arch.h>
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[36df4109] | 36 | #include <arch/arch.h>
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[d8db519] | 37 | #include <typedefs.h>
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| 38 | #include <errno.h>
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| 39 | #include <interrupt.h>
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| 40 | #include <macros.h>
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| 41 | #include <str.h>
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[b169619] | 42 | #include <memw.h>
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[f43d8ce] | 43 | #include <preemption.h>
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[d8db519] | 44 | #include <userspace.h>
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[76d0981d] | 45 | #include <stdbool.h>
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[281b607] | 46 | #include <syscall/syscall.h>
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[06a583e] | 47 | #include <sysinfo/sysinfo.h>
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[d8db519] | 48 | #include <arch/debug.h>
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[5bb8e45] | 49 | #include <arch/debugger.h>
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[ae7ba7b6] | 50 | #include <arch/machine_func.h>
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[973be64e] | 51 |
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[7c3fb9b] | 52 | /*
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| 53 | * Size of the code jumping to the exception handler code
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[96e0748d] | 54 | * - J+NOP
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[ffc277e] | 55 | */
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[96e0748d] | 56 | #define EXCEPTION_JUMP_SIZE 8
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[ffc277e] | 57 |
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[96e0748d] | 58 | #define TLB_EXC ((char *) 0x80000000)
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| 59 | #define NORM_EXC ((char *) 0x80000180)
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| 60 | #define CACHE_EXC ((char *) 0x80000100)
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[ffc277e] | 61 |
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[36df4109] | 62 | static void mips32_pre_mm_init(void);
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| 63 | static void mips32_post_mm_init(void);
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| 64 | static void mips32_post_smp_init(void);
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| 65 |
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| 66 | arch_ops_t mips32_ops = {
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| 67 | .pre_mm_init = mips32_pre_mm_init,
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| 68 | .post_mm_init = mips32_post_mm_init,
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| 69 | .post_smp_init = mips32_post_smp_init,
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| 70 | };
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| 71 |
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| 72 | arch_ops_t *arch_ops = &mips32_ops;
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[8449000] | 73 |
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| 74 | /* Stack pointer saved when entering user mode */
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[d86393c8] | 75 | // FIXME: This won't work with SMP unless thread creation is globally serialized.
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| 76 | uintptr_t supervisor_sp;
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[971cf31f] | 77 |
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[98000fb] | 78 | size_t cpu_count = 0;
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[96e0748d] | 79 |
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[bcad855] | 80 | #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
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| 81 | size_t sdram_size = 0;
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| 82 | #endif
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| 83 |
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[06f96234] | 84 | /** Performs mips32-specific initialization before main_bsp() is called. */
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[36df4109] | 85 | void mips32_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
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[12c7f27] | 86 | {
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[63a045c] | 87 | init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
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[a35b458] | 88 |
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[98000fb] | 89 | size_t i;
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[4872160] | 90 | for (i = 0; i < init.cnt; i++) {
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[63a045c] | 91 | init.tasks[i].paddr = KA2PA(bootinfo->taskmap.tasks[i].addr);
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| 92 | init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
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[f4b1535] | 93 | str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
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[63a045c] | 94 | bootinfo->taskmap.tasks[i].name);
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[96e0748d] | 95 | }
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[a35b458] | 96 |
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[96e0748d] | 97 | for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
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| 98 | if ((bootinfo->cpumap & (1 << i)) != 0)
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| 99 | cpu_count++;
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[971cf31f] | 100 | }
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[bcad855] | 101 |
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| 102 | #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
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| 103 | sdram_size = bootinfo->sdram_size;
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| 104 | #endif
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[260f678] | 105 |
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[dabaa83] | 106 | str_cpy(bargs, CONFIG_BOOT_ARGUMENTS_BUFLEN, bootinfo->bootargs);
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| 107 |
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[260f678] | 108 | /* Initialize machine_ops pointer. */
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| 109 | machine_ops_init();
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[12c7f27] | 110 | }
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| 111 |
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[36df4109] | 112 | void mips32_pre_mm_init(void)
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[f761f1eb] | 113 | {
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[24241cf] | 114 | /* It is not assumed by default */
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[22f7769] | 115 | interrupts_disable();
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[a35b458] | 116 |
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[973be64e] | 117 | /* Initialize dispatch table */
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[7a8c866a] | 118 | exception_init();
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[3156582] | 119 |
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[ffc277e] | 120 | /* Copy the exception vectors to the right places */
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[7688b5d] | 121 | memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
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[0abc2ae] | 122 | smc_coherence(TLB_EXC, EXCEPTION_JUMP_SIZE);
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[7688b5d] | 123 | memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
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[0abc2ae] | 124 | smc_coherence(NORM_EXC, EXCEPTION_JUMP_SIZE);
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[7688b5d] | 125 | memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
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[0abc2ae] | 126 | smc_coherence(CACHE_EXC, EXCEPTION_JUMP_SIZE);
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[a35b458] | 127 |
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[f761f1eb] | 128 | /*
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[c7511ec] | 129 | * Switch to BEV normal level so that exception vectors point to the
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| 130 | * kernel. Clear the error level.
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[f761f1eb] | 131 | */
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[c7511ec] | 132 | cp0_status_write(cp0_status_read() &
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| 133 | ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
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[a35b458] | 134 |
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[6da1013f] | 135 | /*
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| 136 | * Mask all interrupts
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[24241cf] | 137 | */
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| 138 | cp0_mask_all_int();
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[a35b458] | 139 |
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[5bb8e45] | 140 | debugger_init();
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[f761f1eb] | 141 | }
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[7eade45] | 142 |
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[36df4109] | 143 | void mips32_post_mm_init(void)
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[7eade45] | 144 | {
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[7688b5d] | 145 | interrupt_init();
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[260f678] | 146 |
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| 147 | machine_init();
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| 148 | machine_output_init();
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[7eade45] | 149 | }
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[babcb148] | 150 |
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[36df4109] | 151 | void mips32_post_smp_init(void)
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[babcb148] | 152 | {
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[eff1f033] | 153 | /* Set platform name. */
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[ae7ba7b6] | 154 | sysinfo_set_item_data("platform", NULL,
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| 155 | (void *) machine_get_platform_name(),
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| 156 | str_size(machine_get_platform_name()));
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[eff1f033] | 157 |
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[260f678] | 158 | machine_input_init();
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[babcb148] | 159 | }
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[2bd4fdf] | 160 |
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[7f341820] | 161 | void calibrate_delay_loop(void)
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| 162 | {
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| 163 | }
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| 164 |
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[3fcea34] | 165 | uintptr_t arch_get_initial_sp(uintptr_t stack_base, uintptr_t stack_size)
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| 166 | {
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| 167 | return stack_base + stack_size;
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| 168 | }
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| 169 |
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| 170 | void userspace(uintptr_t pc, uintptr_t sp)
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[2bd4fdf] | 171 | {
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[b5ed4f8] | 172 | /* EXL = 1, UM = 1, IE = 1 */
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[2bd4fdf] | 173 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
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[c7511ec] | 174 | cp0_status_um_bit | cp0_status_ie_enabled_bit));
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[3fcea34] | 175 | cp0_epc_write(pc);
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| 176 | userspace_asm(sp, pc);
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[a35b458] | 177 |
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[76d0981d] | 178 | while (true)
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[1433ecda] | 179 | ;
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[2bd4fdf] | 180 | }
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| 181 |
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[39cea6a] | 182 | /** Perform mips32 specific tasks needed before the new task is run. */
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| 183 | void before_task_runs_arch(void)
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| 184 | {
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| 185 | }
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| 186 |
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| 187 | /** Perform mips32 specific tasks needed before the new thread is scheduled. */
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[2bd4fdf] | 188 | void before_thread_runs_arch(void)
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| 189 | {
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[26aafe8] | 190 | supervisor_sp =
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[2277e03] | 191 | (uintptr_t) &THREAD->kstack[STACK_SIZE];
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[2bd4fdf] | 192 | }
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[97f1691] | 193 |
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| 194 | void after_thread_ran_arch(void)
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| 195 | {
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| 196 | }
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[281b607] | 197 |
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[f74bbaf] | 198 | void arch_reboot(void)
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| 199 | {
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[edebc15c] | 200 | ___halt();
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[76d0981d] | 201 | while (true)
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[1433ecda] | 202 | ;
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[6da1013f] | 203 | }
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| 204 |
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| 205 | /** Construct function pointer
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| 206 | *
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| 207 | * @param fptr function pointer structure
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| 208 | * @param addr function address
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| 209 | * @param caller calling function address
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| 210 | *
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| 211 | * @return address of the function pointer
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| 212 | *
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| 213 | */
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| 214 | void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
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| 215 | {
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| 216 | return addr;
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[f74bbaf] | 217 | }
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| 218 |
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[3a2f8aa] | 219 | void irq_initialize_arch(irq_t *irq)
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| 220 | {
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| 221 | (void) irq;
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| 222 | }
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| 223 |
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[d227101] | 224 | /** @}
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[b45c443] | 225 | */
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