source: mainline/kernel/arch/mips32/src/interrupt.c@ 54171e8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 54171e8 was da1bafb, checked in by Martin Decky <martin@…>, 16 years ago

major code revision

  • replace spinlocks taken with interrupts disabled with irq_spinlocks
  • change spacing (not indendation) to be tab-size independent
  • use unsigned integer types where appropriate (especially bit flags)
  • visual separation
  • remove argument names in function prototypes
  • string changes
  • correct some formating directives
  • replace various cryptic single-character variables (t, a, m, c, b, etc.) with proper identifiers (thread, task, timeout, as, itm, itc, etc.)
  • unify some assembler constructs
  • unused page table levels are now optimized out in compile time
  • replace several ints (with boolean semantics) with bools
  • use specifically sized types instead of generic types where appropriate (size_t, uint32_t, btree_key_t)
  • improve comments
  • split asserts with conjuction into multiple independent asserts
  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <interrupt.h>
36#include <arch/interrupt.h>
37#include <typedefs.h>
38#include <arch.h>
39#include <arch/cp0.h>
40#include <time/clock.h>
41#include <ipc/sysipc.h>
42#include <ddi/device.h>
43
44#define IRQ_COUNT 8
45#define TIMER_IRQ 7
46#define DORDER_IRQ 5
47
48function virtual_timer_fnc = NULL;
49static irq_t timer_irq;
50
51// TODO: This is SMP unsafe!!!
52
53uint32_t count_hi = 0;
54static unsigned long nextcount;
55static unsigned long lastcount;
56
57/** Disable interrupts.
58 *
59 * @return Old interrupt priority level.
60 */
61ipl_t interrupts_disable(void)
62{
63 ipl_t ipl = (ipl_t) cp0_status_read();
64 cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
65 return ipl;
66}
67
68/** Enable interrupts.
69 *
70 * @return Old interrupt priority level.
71 */
72ipl_t interrupts_enable(void)
73{
74 ipl_t ipl = (ipl_t) cp0_status_read();
75 cp0_status_write(ipl | cp0_status_ie_enabled_bit);
76 return ipl;
77}
78
79/** Restore interrupt priority level.
80 *
81 * @param ipl Saved interrupt priority level.
82 */
83void interrupts_restore(ipl_t ipl)
84{
85 cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
86}
87
88/** Read interrupt priority level.
89 *
90 * @return Current interrupt priority level.
91 */
92ipl_t interrupts_read(void)
93{
94 return cp0_status_read();
95}
96
97/** Check interrupts state.
98 *
99 * @return True if interrupts are disabled.
100 *
101 */
102bool interrupts_disabled(void)
103{
104 return !(cp0_status_read() & cp0_status_ie_enabled_bit);
105}
106
107/** Start hardware clock
108 *
109 */
110static void timer_start(void)
111{
112 lastcount = cp0_count_read();
113 nextcount = cp0_compare_value + cp0_count_read();
114 cp0_compare_write(nextcount);
115}
116
117static irq_ownership_t timer_claim(irq_t *irq)
118{
119 return IRQ_ACCEPT;
120}
121
122static void timer_irq_handler(irq_t *irq)
123{
124 if (cp0_count_read() < lastcount)
125 /* Count overflow detected */
126 count_hi++;
127
128 lastcount = cp0_count_read();
129
130 unsigned long drift = cp0_count_read() - nextcount;
131 while (drift > cp0_compare_value) {
132 drift -= cp0_compare_value;
133 CPU->missed_clock_ticks++;
134 }
135
136 nextcount = cp0_count_read() + cp0_compare_value - drift;
137 cp0_compare_write(nextcount);
138
139 /*
140 * We are holding a lock which prevents preemption.
141 * Release the lock, call clock() and reacquire the lock again.
142 */
143 irq_spinlock_unlock(&irq->lock, false);
144 clock();
145 irq_spinlock_lock(&irq->lock, false);
146
147 if (virtual_timer_fnc != NULL)
148 virtual_timer_fnc();
149}
150
151/* Initialize basic tables for exception dispatching */
152void interrupt_init(void)
153{
154 irq_init(IRQ_COUNT, IRQ_COUNT);
155
156 irq_initialize(&timer_irq);
157 timer_irq.devno = device_assign_devno();
158 timer_irq.inr = TIMER_IRQ;
159 timer_irq.claim = timer_claim;
160 timer_irq.handler = timer_irq_handler;
161 irq_register(&timer_irq);
162
163 timer_start();
164 cp0_unmask_int(TIMER_IRQ);
165}
166
167/** @}
168 */
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