source: mainline/kernel/arch/mips32/src/interrupt.c@ 71eef11

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 71eef11 was 8df2eab, checked in by Martin Decky <martin@…>, 18 years ago

fix trivial bug in storing lastcount

  • Property mode set to 100644
File size: 4.0 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[9a5b556]29/** @addtogroup mips32interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[973be64e]35#include <interrupt.h>
[f761f1eb]36#include <arch/interrupt.h>
37#include <arch/types.h>
38#include <arch.h>
39#include <arch/cp0.h>
40#include <time/clock.h>
[3156582]41#include <arch/drivers/arc.h>
[5626277]42#include <ipc/sysipc.h>
[7688b5d]43#include <ddi/device.h>
44
45#define IRQ_COUNT 8
46#define TIMER_IRQ 7
47
[8c84448]48function virtual_timer_fnc = NULL;
[7688b5d]49static irq_t timer_irq;
[5626277]50
[22f7769]51/** Disable interrupts.
52 *
53 * @return Old interrupt priority level.
54 */
55ipl_t interrupts_disable(void)
[f761f1eb]56{
[22f7769]57 ipl_t ipl = (ipl_t) cp0_status_read();
58 cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
59 return ipl;
[f761f1eb]60}
61
[22f7769]62/** Enable interrupts.
63 *
64 * @return Old interrupt priority level.
65 */
66ipl_t interrupts_enable(void)
[f761f1eb]67{
[22f7769]68 ipl_t ipl = (ipl_t) cp0_status_read();
69 cp0_status_write(ipl | cp0_status_ie_enabled_bit);
70 return ipl;
[f761f1eb]71}
72
[22f7769]73/** Restore interrupt priority level.
74 *
75 * @param ipl Saved interrupt priority level.
76 */
77void interrupts_restore(ipl_t ipl)
[f761f1eb]78{
[22f7769]79 cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
[f761f1eb]80}
81
[22f7769]82/** Read interrupt priority level.
83 *
84 * @return Current interrupt priority level.
85 */
86ipl_t interrupts_read(void)
[f761f1eb]87{
[76cec1e]88 return cp0_status_read();
[f761f1eb]89}
90
[d6e5cbc]91/* TODO: This is SMP unsafe!!! */
[0287820]92uint32_t count_hi = 0;
[d6e5cbc]93static unsigned long nextcount;
[0287820]94static unsigned long lastcount;
95
[d6e5cbc]96/** Start hardware clock */
97static void timer_start(void)
98{
[0287820]99 lastcount = cp0_count_read();
[d6e5cbc]100 nextcount = cp0_compare_value + cp0_count_read();
101 cp0_compare_write(nextcount);
102}
103
[7688b5d]104static irq_ownership_t timer_claim(void)
105{
106 return IRQ_ACCEPT;
107}
108
109static void timer_irq_handler(irq_t *irq, void *arg, ...)
[973be64e]110{
[d6e5cbc]111 unsigned long drift;
[0287820]112
[8df2eab]113 if (cp0_count_read() < lastcount)
114 /* Count overflow detected */
[0287820]115 count_hi++;
[8df2eab]116 lastcount = cp0_count_read();
[0287820]117
[d6e5cbc]118 drift = cp0_count_read() - nextcount;
119 while (drift > cp0_compare_value) {
120 drift -= cp0_compare_value;
121 CPU->missed_clock_ticks++;
122 }
123 nextcount = cp0_count_read() + cp0_compare_value - drift;
124 cp0_compare_write(nextcount);
[0287820]125
[f619ec11]126 /*
127 * We are holding a lock which prevents preemption.
128 * Release the lock, call clock() and reacquire the lock again.
129 */
130 spinlock_unlock(&irq->lock);
[973be64e]131 clock();
[f619ec11]132 spinlock_lock(&irq->lock);
[7688b5d]133
[8c84448]134 if (virtual_timer_fnc != NULL)
135 virtual_timer_fnc();
[973be64e]136}
137
138/* Initialize basic tables for exception dispatching */
139void interrupt_init(void)
140{
[7688b5d]141 irq_init(IRQ_COUNT, IRQ_COUNT);
142
143 irq_initialize(&timer_irq);
144 timer_irq.devno = device_assign_devno();
145 timer_irq.inr = TIMER_IRQ;
146 timer_irq.claim = timer_claim;
147 timer_irq.handler = timer_irq_handler;
148 irq_register(&timer_irq);
149
[d6e5cbc]150 timer_start();
[7688b5d]151 cp0_unmask_int(TIMER_IRQ);
[5626277]152}
[b45c443]153
[9a5b556]154/** @}
[b45c443]155 */
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