| [f761f1eb] | 1 | /*
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| [df4ed85] | 2 | * Copyright (c) 2003-2004 Jakub Jermar
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| [f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| [9a5b556] | 29 | /** @addtogroup mips32interrupt
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| [b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| [973be64e] | 35 | #include <interrupt.h>
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| [f761f1eb] | 36 | #include <arch/interrupt.h>
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| [d99c1d2] | 37 | #include <typedefs.h>
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| [f761f1eb] | 38 | #include <arch.h>
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| 39 | #include <arch/cp0.h>
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| 40 | #include <time/clock.h>
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| [5626277] | 41 | #include <ipc/sysipc.h>
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| [7688b5d] | 42 | #include <ddi/device.h>
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| 43 |
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| [7f341820] | 44 | #define IRQ_COUNT 8
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| 45 | #define TIMER_IRQ 7
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| 46 | #define DORDER_IRQ 5
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| [7688b5d] | 47 |
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| [8c84448] | 48 | function virtual_timer_fnc = NULL;
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| [7688b5d] | 49 | static irq_t timer_irq;
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| [5626277] | 50 |
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| [da1bafb] | 51 | // TODO: This is SMP unsafe!!!
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| 52 |
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| 53 | uint32_t count_hi = 0;
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| 54 | static unsigned long nextcount;
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| 55 | static unsigned long lastcount;
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| 56 |
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| [22f7769] | 57 | /** Disable interrupts.
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| 58 | *
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| 59 | * @return Old interrupt priority level.
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| 60 | */
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| 61 | ipl_t interrupts_disable(void)
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| [f761f1eb] | 62 | {
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| [22f7769] | 63 | ipl_t ipl = (ipl_t) cp0_status_read();
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| 64 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
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| 65 | return ipl;
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| [f761f1eb] | 66 | }
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| 67 |
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| [22f7769] | 68 | /** Enable interrupts.
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| 69 | *
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| 70 | * @return Old interrupt priority level.
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| 71 | */
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| 72 | ipl_t interrupts_enable(void)
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| [f761f1eb] | 73 | {
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| [22f7769] | 74 | ipl_t ipl = (ipl_t) cp0_status_read();
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| 75 | cp0_status_write(ipl | cp0_status_ie_enabled_bit);
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| 76 | return ipl;
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| [f761f1eb] | 77 | }
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| 78 |
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| [22f7769] | 79 | /** Restore interrupt priority level.
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| 80 | *
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| 81 | * @param ipl Saved interrupt priority level.
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| 82 | */
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| 83 | void interrupts_restore(ipl_t ipl)
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| [f761f1eb] | 84 | {
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| [22f7769] | 85 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
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| [f761f1eb] | 86 | }
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| 87 |
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| [22f7769] | 88 | /** Read interrupt priority level.
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| 89 | *
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| 90 | * @return Current interrupt priority level.
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| 91 | */
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| 92 | ipl_t interrupts_read(void)
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| [f761f1eb] | 93 | {
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| [76cec1e] | 94 | return cp0_status_read();
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| [f761f1eb] | 95 | }
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| 96 |
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| [b7aa7c5] | 97 | /** Check interrupts state.
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| 98 | *
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| 99 | * @return True if interrupts are disabled.
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| 100 | *
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| 101 | */
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| 102 | bool interrupts_disabled(void)
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| 103 | {
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| 104 | return !(cp0_status_read() & cp0_status_ie_enabled_bit);
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| 105 | }
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| 106 |
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| [da1bafb] | 107 | /** Start hardware clock
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| 108 | *
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| 109 | */
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| [d6e5cbc] | 110 | static void timer_start(void)
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| 111 | {
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| [0287820] | 112 | lastcount = cp0_count_read();
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| [d6e5cbc] | 113 | nextcount = cp0_compare_value + cp0_count_read();
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| 114 | cp0_compare_write(nextcount);
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| 115 | }
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| 116 |
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| [c9b550b] | 117 | static irq_ownership_t timer_claim(irq_t *irq)
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| [7688b5d] | 118 | {
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| 119 | return IRQ_ACCEPT;
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| 120 | }
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| 121 |
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| [6cd9aa6] | 122 | static void timer_irq_handler(irq_t *irq)
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| [973be64e] | 123 | {
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| [8df2eab] | 124 | if (cp0_count_read() < lastcount)
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| 125 | /* Count overflow detected */
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| [0287820] | 126 | count_hi++;
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| [da1bafb] | 127 |
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| [8df2eab] | 128 | lastcount = cp0_count_read();
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| [0287820] | 129 |
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| [da1bafb] | 130 | unsigned long drift = cp0_count_read() - nextcount;
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| [d6e5cbc] | 131 | while (drift > cp0_compare_value) {
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| 132 | drift -= cp0_compare_value;
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| 133 | CPU->missed_clock_ticks++;
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| 134 | }
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| [da1bafb] | 135 |
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| [d6e5cbc] | 136 | nextcount = cp0_count_read() + cp0_compare_value - drift;
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| 137 | cp0_compare_write(nextcount);
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| [0287820] | 138 |
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| [f619ec11] | 139 | /*
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| 140 | * We are holding a lock which prevents preemption.
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| 141 | * Release the lock, call clock() and reacquire the lock again.
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| 142 | */
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| [da1bafb] | 143 | irq_spinlock_unlock(&irq->lock, false);
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| [973be64e] | 144 | clock();
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| [da1bafb] | 145 | irq_spinlock_lock(&irq->lock, false);
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| [7688b5d] | 146 |
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| [8c84448] | 147 | if (virtual_timer_fnc != NULL)
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| 148 | virtual_timer_fnc();
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| [973be64e] | 149 | }
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| 150 |
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| 151 | /* Initialize basic tables for exception dispatching */
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| 152 | void interrupt_init(void)
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| 153 | {
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| [7688b5d] | 154 | irq_init(IRQ_COUNT, IRQ_COUNT);
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| 155 |
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| 156 | irq_initialize(&timer_irq);
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| 157 | timer_irq.devno = device_assign_devno();
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| 158 | timer_irq.inr = TIMER_IRQ;
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| 159 | timer_irq.claim = timer_claim;
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| 160 | timer_irq.handler = timer_irq_handler;
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| 161 | irq_register(&timer_irq);
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| 162 |
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| [d6e5cbc] | 163 | timer_start();
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| [7688b5d] | 164 | cp0_unmask_int(TIMER_IRQ);
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| [5626277] | 165 | }
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| [b45c443] | 166 |
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| [9a5b556] | 167 | /** @}
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| [b45c443] | 168 | */
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