source: mainline/kernel/arch/mips32/src/exception.c@ 7cd7a8d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7cd7a8d was 7c3fb9b, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix block comment formatting (ccheck).
  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*
2 * Copyright (c) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/exception.h>
36#include <arch/interrupt.h>
37#include <arch/mm/tlb.h>
38#include <panic.h>
39#include <arch/cp0.h>
40#include <arch.h>
41#include <assert.h>
42#include <proc/thread.h>
43#include <print.h>
44#include <interrupt.h>
45#include <halt.h>
46#include <ddi/irq.h>
47#include <arch/debugger.h>
48#include <symtab.h>
49#include <log.h>
50
51static const char *exctable[] = {
52 "Interrupt",
53 "TLB Modified",
54 "TLB Invalid",
55 "TLB Invalid Store",
56 "Address Error - load/instr. fetch",
57 "Address Error - store",
58 "Bus Error - fetch instruction",
59 "Bus Error - data reference",
60 "Syscall",
61 "BreakPoint",
62 "Reserved Instruction",
63 "Coprocessor Unusable",
64 "Arithmetic Overflow",
65 "Trap",
66 "Virtual Coherency - instruction",
67 "Floating Point",
68 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
69 "WatchHi/WatchLo", /* 23 */
70 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
71 "Virtual Coherency - data",
72};
73
74void istate_decode(istate_t *istate)
75{
76 log_printf("epc=%#010" PRIx32 "\tsta=%#010" PRIx32 "\t"
77 "lo =%#010" PRIx32 "\thi =%#010" PRIx32 "\n",
78 istate->epc, istate->status, istate->lo, istate->hi);
79
80 log_printf("a0 =%#010" PRIx32 "\ta1 =%#010" PRIx32 "\t"
81 "a2 =%#010" PRIx32 "\ta3 =%#010" PRIx32 "\n",
82 istate->a0, istate->a1, istate->a2, istate->a3);
83
84 log_printf("t0 =%#010" PRIx32 "\tt1 =%#010" PRIx32 "\t"
85 "t2 =%#010" PRIx32 "\tt3 =%#010" PRIx32 "\n",
86 istate->t0, istate->t1, istate->t2, istate->t3);
87
88 log_printf("t4 =%#010" PRIx32 "\tt5 =%#010" PRIx32 "\t"
89 "t6 =%#010" PRIx32 "\tt7 =%#010" PRIx32 "\n",
90 istate->t4, istate->t5, istate->t6, istate->t7);
91
92 log_printf("t8 =%#010" PRIx32 "\tt9 =%#010" PRIx32 "\t"
93 "v0 =%#010" PRIx32 "\tv1 =%#010" PRIx32 "\n",
94 istate->t8, istate->t9, istate->v0, istate->v1);
95
96 log_printf("s0 =%#010" PRIx32 "\ts1 =%#010" PRIx32 "\t"
97 "s2 =%#010" PRIx32 "\ts3 =%#010" PRIx32 "\n",
98 istate->s0, istate->s1, istate->s2, istate->s3);
99
100 log_printf("s4 =%#010" PRIx32 "\ts5 =%#010" PRIx32 "\t"
101 "s6 =%#010" PRIx32 "\ts7 =%#010" PRIx32 "\n",
102 istate->s4, istate->s5, istate->s6, istate->s7);
103
104 log_printf("s8 =%#010" PRIx32 "\tat =%#010" PRIx32 "\t"
105 "kt0=%#010" PRIx32 "\tkt1=%#010" PRIx32 "\n",
106 istate->s8, istate->at, istate->kt0, istate->kt1);
107
108 log_printf("sp =%#010" PRIx32 "\tra =%#010" PRIx32 "\t"
109 "gp =%#010" PRIx32 "\n",
110 istate->sp, istate->ra, istate->gp);
111}
112
113static void unhandled_exception(unsigned int n, istate_t *istate)
114{
115 fault_if_from_uspace(istate, "Unhandled exception %s.", exctable[n]);
116 panic_badtrap(istate, n, "Unhandled exception %s.", exctable[n]);
117}
118
119static void reserved_instr_exception(unsigned int n, istate_t *istate)
120{
121 if (*((uint32_t *) istate->epc) == 0x7c03e83b) {
122 assert(THREAD);
123 istate->epc += 4;
124 istate->v1 = istate->kt1;
125 } else
126 unhandled_exception(n, istate);
127}
128
129static void breakpoint_exception(unsigned int n, istate_t *istate)
130{
131#ifdef CONFIG_DEBUG
132 debugger_bpoint(istate);
133#else
134 /*
135 * It is necessary to not re-execute BREAK instruction after
136 * returning from Exception handler
137 * (see page 138 in R4000 Manual for more information)
138 */
139 istate->epc += 4;
140#endif
141}
142
143static void tlbmod_exception(unsigned int n, istate_t *istate)
144{
145 tlb_modified(istate);
146}
147
148static void tlbinv_exception(unsigned int n, istate_t *istate)
149{
150 tlb_invalid(istate);
151}
152
153#ifdef CONFIG_FPU_LAZY
154static void cpuns_exception(unsigned int n, istate_t *istate)
155{
156 if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id)
157 scheduler_fpu_lazy_request();
158 else {
159 fault_if_from_uspace(istate,
160 "Unhandled Coprocessor Unusable Exception.");
161 panic_badtrap(istate, n,
162 "Unhandled Coprocessor Unusable Exception.");
163 }
164}
165#endif
166
167static void interrupt_exception(unsigned int n, istate_t *istate)
168{
169 uint32_t ip;
170 uint32_t im;
171
172 /* Decode interrupt number and process the interrupt */
173 ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift;
174 im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift;
175
176 unsigned int i;
177 for (i = 0; i < 8; i++) {
178
179 /*
180 * The interrupt could only occur if it is unmasked in the
181 * status register. On the other hand, an interrupt can be
182 * apparently pending even if it is masked, so we need to
183 * check both the masked and pending interrupts.
184 */
185 if (im & ip & (1 << i)) {
186 irq_t *irq = irq_dispatch_and_lock(i);
187 if (irq) {
188 /*
189 * The IRQ handler was found.
190 */
191 irq->handler(irq);
192 irq_spinlock_unlock(&irq->lock, false);
193 } else {
194 /*
195 * Spurious interrupt.
196 */
197#ifdef CONFIG_DEBUG
198 log(LF_ARCH, LVL_DEBUG,
199 "cpu%u: spurious interrupt (inum=%u)",
200 CPU->id, i);
201#endif
202 }
203 }
204 }
205}
206
207/** Handle syscall userspace call */
208static void syscall_exception(unsigned int n, istate_t *istate)
209{
210 fault_if_from_uspace(istate, "Syscall is handled through shortcut.");
211}
212
213void exception_init(void)
214{
215 unsigned int i;
216
217 /* Clear exception table */
218 for (i = 0; i < IVT_ITEMS; i++)
219 exc_register(i, "undef", false,
220 (iroutine_t) unhandled_exception);
221
222 exc_register(EXC_Bp, "bkpoint", true,
223 (iroutine_t) breakpoint_exception);
224 exc_register(EXC_RI, "resinstr", true,
225 (iroutine_t) reserved_instr_exception);
226 exc_register(EXC_Mod, "tlb_mod", true,
227 (iroutine_t) tlbmod_exception);
228 exc_register(EXC_TLBL, "tlbinvl", true,
229 (iroutine_t) tlbinv_exception);
230 exc_register(EXC_TLBS, "tlbinvl", true,
231 (iroutine_t) tlbinv_exception);
232 exc_register(EXC_Int, "interrupt", true,
233 (iroutine_t) interrupt_exception);
234
235#ifdef CONFIG_FPU_LAZY
236 exc_register(EXC_CpU, "cpunus", true,
237 (iroutine_t) cpuns_exception);
238#endif
239
240 exc_register(EXC_Sys, "syscall", true,
241 (iroutine_t) syscall_exception);
242}
243
244/** @}
245 */
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