source: mainline/kernel/arch/mips32/src/exception.c@ 4fe907b9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4fe907b9 was 22a28a69, checked in by Jakub Jermar <jakub@…>, 15 years ago

Rename decode_istate() to istate_decode() and declare it only once in
the generic interrupt.h.

  • Property mode set to 100644
File size: 5.8 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[da1bafb]29/** @addtogroup mips32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch/exception.h>
[9c0a9b3]36#include <arch/interrupt.h>
[b3f8fb7]37#include <arch/mm/tlb.h>
[f761f1eb]38#include <panic.h>
39#include <arch/cp0.h>
[d99c1d2]40#include <typedefs.h>
[f761f1eb]41#include <arch.h>
[623ba26c]42#include <debug.h>
[1084a784]43#include <proc/thread.h>
[7a8c866a]44#include <print.h>
45#include <interrupt.h>
[e07fe0c]46#include <func.h>
[7688b5d]47#include <ddi/irq.h>
[5bb8e45]48#include <arch/debugger.h>
[e2b762ec]49#include <symtab.h>
50
[a000878c]51static const char *exctable[] = {
[2f40fe4]52 "Interrupt",
53 "TLB Modified",
54 "TLB Invalid",
55 "TLB Invalid Store",
56 "Address Error - load/instr. fetch",
57 "Address Error - store",
58 "Bus Error - fetch instruction",
59 "Bus Error - data reference",
60 "Syscall",
61 "BreakPoint",
62 "Reserved Instruction",
63 "Coprocessor Unusable",
64 "Arithmetic Overflow",
65 "Trap",
66 "Virtual Coherency - instruction",
67 "Floating Point",
68 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
[da1bafb]69 "WatchHi/WatchLo", /* 23 */
[2f40fe4]70 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
71 "Virtual Coherency - data",
[7a8c866a]72};
73
[22a28a69]74void istate_decode(istate_t *istate)
[7a8c866a]75{
[ac11ac7]76 printf("at=%p\tv0=%p\tv1=%p\n", istate->at, istate->v0, istate->v1);
77 printf("a0=%p\ta1=%p\ta2=%p\n", istate->a0, istate->a1, istate->a2);
78 printf("a3=%p\tt0=%p\tt1=%p\n", istate->a3, istate->t0, istate->t1);
79 printf("t2=%p\tt3=%p\tt4=%p\n", istate->t2, istate->t3, istate->t4);
80 printf("t5=%p\tt6=%p\tt7=%p\n", istate->t5, istate->t6, istate->t7);
81 printf("t8=%p\tt9=%p\tgp=%p\n", istate->t8, istate->t9, istate->gp);
82 printf("sp=%p\tra=%p\t\n", istate->sp, istate->ra);
83 printf("lo=%p\thi=%p\t\n", istate->lo, istate->hi);
84 printf("cp0_status=%p\tcp0_epc=%p\tk1=%p\n",
85 istate->status, istate->epc, istate->k1);
[7a8c866a]86}
87
[214ec25c]88static void unhandled_exception(unsigned int n, istate_t *istate)
[7a8c866a]89{
[f651e80]90 fault_if_from_uspace(istate, "Unhandled exception %s.", exctable[n]);
[ac11ac7]91 panic_badtrap(istate, n, "Unhandled exception %s.", exctable[n]);
[7a8c866a]92}
93
[214ec25c]94static void reserved_instr_exception(unsigned int n, istate_t *istate)
[3b712407]95{
[a000878c]96 if (*((uint32_t *) istate->epc) == 0x7c03e83b) {
[3b712407]97 ASSERT(THREAD);
98 istate->epc += 4;
99 istate->v1 = istate->k1;
[a000878c]100 } else
[5201199]101 unhandled_exception(n, istate);
[3b712407]102}
103
[214ec25c]104static void breakpoint_exception(unsigned int n, istate_t *istate)
[7a8c866a]105{
[5bb8e45]106#ifdef CONFIG_DEBUG
[25d7709]107 debugger_bpoint(istate);
[5bb8e45]108#else
[7a8c866a]109 /* it is necessary to not re-execute BREAK instruction after
110 returning from Exception handler
111 (see page 138 in R4000 Manual for more information) */
[25d7709]112 istate->epc += 4;
[5bb8e45]113#endif
[7a8c866a]114}
115
[214ec25c]116static void tlbmod_exception(unsigned int n, istate_t *istate)
[7a8c866a]117{
[25d7709]118 tlb_modified(istate);
[7a8c866a]119}
120
[214ec25c]121static void tlbinv_exception(unsigned int n, istate_t *istate)
[7a8c866a]122{
[25d7709]123 tlb_invalid(istate);
[7a8c866a]124}
125
[5a95b25]126#ifdef CONFIG_FPU_LAZY
[214ec25c]127static void cpuns_exception(unsigned int n, istate_t *istate)
[7a8c866a]128{
129 if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id)
130 scheduler_fpu_lazy_request();
[874621f]131 else {
[ac11ac7]132 fault_if_from_uspace(istate,
133 "Unhandled Coprocessor Unusable Exception.");
134 panic_badtrap(istate, n,
135 "Unhandled Coprocessor Unusable Exception.");
[874621f]136 }
[7a8c866a]137}
[5a95b25]138#endif
[7a8c866a]139
[214ec25c]140static void interrupt_exception(unsigned int n, istate_t *istate)
[7a8c866a]141{
[da1bafb]142 /* Decode interrupt number and process the interrupt */
143 uint32_t cause = (cp0_cause_read() >> 8) & 0xff;
[7a8c866a]144
[da1bafb]145 unsigned int i;
[7688b5d]146 for (i = 0; i < 8; i++) {
147 if (cause & (1 << i)) {
148 irq_t *irq = irq_dispatch_and_lock(i);
149 if (irq) {
150 /*
151 * The IRQ handler was found.
152 */
[6cd9aa6]153 irq->handler(irq);
[da1bafb]154 irq_spinlock_unlock(&irq->lock, false);
[7688b5d]155 } else {
156 /*
157 * Spurious interrupt.
158 */
159#ifdef CONFIG_DEBUG
[214ec25c]160 printf("cpu%u: spurious interrupt (inum=%u)\n",
[6cd9aa6]161 CPU->id, i);
[7688b5d]162#endif
163 }
164 }
165 }
[7a8c866a]166}
167
[1b109cb]168/** Handle syscall userspace call */
[214ec25c]169static void syscall_exception(unsigned int n, istate_t *istate)
[f761f1eb]170{
[ac11ac7]171 fault_if_from_uspace(istate, "Syscall is handled through shortcut.");
[f761f1eb]172}
[7a8c866a]173
174void exception_init(void)
175{
[b3b7e14a]176 unsigned int i;
[da1bafb]177
[7a8c866a]178 /* Clear exception table */
[7688b5d]179 for (i = 0; i < IVT_ITEMS; i++)
[b3b7e14a]180 exc_register(i, "undef", false,
181 (iroutine_t) unhandled_exception);
182
183 exc_register(EXC_Bp, "bkpoint", true,
184 (iroutine_t) breakpoint_exception);
185 exc_register(EXC_RI, "resinstr", true,
186 (iroutine_t) reserved_instr_exception);
187 exc_register(EXC_Mod, "tlb_mod", true,
188 (iroutine_t) tlbmod_exception);
189 exc_register(EXC_TLBL, "tlbinvl", true,
190 (iroutine_t) tlbinv_exception);
191 exc_register(EXC_TLBS, "tlbinvl", true,
192 (iroutine_t) tlbinv_exception);
193 exc_register(EXC_Int, "interrupt", true,
194 (iroutine_t) interrupt_exception);
[7688b5d]195
[7a8c866a]196#ifdef CONFIG_FPU_LAZY
[b3b7e14a]197 exc_register(EXC_CpU, "cpunus", true,
198 (iroutine_t) cpuns_exception);
[7a8c866a]199#endif
[b3b7e14a]200
201 exc_register(EXC_Sys, "syscall", true,
202 (iroutine_t) syscall_exception);
[7a8c866a]203}
[b45c443]204
[3c5006a0]205/** @}
[b45c443]206 */
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