[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2003-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[1bb2e7a] | 29 | /** @addtogroup mips32
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[f761f1eb] | 35 | #include <arch/cpu.h>
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| 36 | #include <cpu.h>
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| 37 | #include <arch.h>
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| 38 | #include <arch/cp0.h>
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[38de8a5] | 39 | #include <print.h>
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[f761f1eb] | 40 |
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[38de8a5] | 41 | struct data_t {
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[f761f1eb] | 42 | char *vendor;
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| 43 | char *model;
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[38de8a5] | 44 | };
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| 45 |
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| 46 | static struct data_t imp_data[] = {
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[76cec1e] | 47 | { "Invalid", "Invalid" }, /* 0x00 */
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| 48 | { "MIPS", "R2000" }, /* 0x01 */
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| 49 | { "MIPS", "R3000" }, /* 0x02 */
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| 50 | { "MIPS", "R6000" }, /* 0x03 */
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| 51 | { "MIPS", " R4000/R4400" }, /* 0x04 */
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| 52 | { "LSI Logic", "R3000" }, /* 0x05 */
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| 53 | { "MIPS", "R6000A" }, /* 0x06 */
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| 54 | { "IDT", "3051/3052" }, /* 0x07 */
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| 55 | { "Invalid", "Invalid" }, /* 0x08 */
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| 56 | { "MIPS", "R10000/T5" }, /* 0x09 */
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| 57 | { "MIPS", "R4200" }, /* 0x0a */
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| 58 | { "Unknown", "Unknown" }, /* 0x0b */
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| 59 | { "Unknown", "Unknown" }, /* 0x0c */
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| 60 | { "Invalid", "Invalid" }, /* 0x0d */
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| 61 | { "Invalid", "Invalid" }, /* 0x0e */
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| 62 | { "Invalid", "Invalid" }, /* 0x0f */
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| 63 | { "MIPS", "R8000" }, /* 0x10 */
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| 64 | { "Invalid", "Invalid" }, /* 0x11 */
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| 65 | { "Invalid", "Invalid" }, /* 0x12 */
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| 66 | { "Invalid", "Invalid" }, /* 0x13 */
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| 67 | { "Invalid", "Invalid" }, /* 0x14 */
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| 68 | { "Invalid", "Invalid" }, /* 0x15 */
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| 69 | { "Invalid", "Invalid" }, /* 0x16 */
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| 70 | { "Invalid", "Invalid" }, /* 0x17 */
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| 71 | { "Invalid", "Invalid" }, /* 0x18 */
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| 72 | { "Invalid", "Invalid" }, /* 0x19 */
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| 73 | { "Invalid", "Invalid" }, /* 0x1a */
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| 74 | { "Invalid", "Invalid" }, /* 0x1b */
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| 75 | { "Invalid", "Invalid" }, /* 0x1c */
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| 76 | { "Invalid", "Invalid" }, /* 0x1d */
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| 77 | { "Invalid", "Invalid" }, /* 0x1e */
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| 78 | { "Invalid", "Invalid" }, /* 0x1f */
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| 79 | { "QED", "R4600" }, /* 0x20 */
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| 80 | { "Sony", "R3000" }, /* 0x21 */
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| 81 | { "Toshiba", "R3000" }, /* 0x22 */
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[24241cf] | 82 | { "NKK", "R3000" }, /* 0x23 */
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| 83 | { NULL, NULL }
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[f761f1eb] | 84 | };
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| 85 |
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[38de8a5] | 86 | static struct data_t imp_data80[] = {
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| 87 | { "MIPS", "4Kc" }, /* 0x80 */
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| 88 | {"Invalid","Invalid"}, /* 0x81 */
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| 89 | {"Invalid","Invalid"}, /* 0x82 */
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[24241cf] | 90 | {"MIPS","4Km & 4Kp"}, /* 0x83 */
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| 91 | { NULL, NULL}
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[38de8a5] | 92 | };
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| 93 |
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[f761f1eb] | 94 | void cpu_arch_init(void)
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| 95 | {
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| 96 | }
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| 97 |
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| 98 | void cpu_identify(void)
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| 99 | {
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[43114c5] | 100 | CPU->arch.rev_num = cp0_prid_read() & 0xff;
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| 101 | CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
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[f761f1eb] | 102 | }
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| 103 |
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| 104 | void cpu_print_report(cpu_t *m)
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| 105 | {
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[38de8a5] | 106 | struct data_t *data;
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[6c441cf8] | 107 | unsigned int i;
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[38de8a5] | 108 |
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| 109 | if (m->arch.imp_num & 0x80) {
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[24241cf] | 110 | /* Count records */
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[6c441cf8] | 111 | for (i = 0; imp_data80[i].vendor; i++);
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[fbe058f] | 112 | if ((m->arch.imp_num & 0x7f) >= i) {
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[6c441cf8] | 113 | printf("imp=%d\n", m->arch.imp_num);
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[24241cf] | 114 | return;
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| 115 | }
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[38de8a5] | 116 | data = &imp_data80[m->arch.imp_num & 0x7f];
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[24241cf] | 117 | } else {
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[6c441cf8] | 118 | for (i = 0; imp_data[i].vendor; i++);
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[24241cf] | 119 | if (m->arch.imp_num >= i) {
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[6c441cf8] | 120 | printf("imp=%d\n", m->arch.imp_num);
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[24241cf] | 121 | return;
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| 122 | }
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[38de8a5] | 123 | data = &imp_data[m->arch.imp_num];
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[24241cf] | 124 | }
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[38de8a5] | 125 |
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[f761f1eb] | 126 | printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n",
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[38de8a5] | 127 | m->id, data->vendor, data->model, m->arch.rev_num >> 4,
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[6c441cf8] | 128 | m->arch.rev_num & 0xf, m->arch.imp_num);
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[f761f1eb] | 129 | }
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[b45c443] | 130 |
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[1bb2e7a] | 131 | /** @}
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[b45c443] | 132 | */
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