source: mainline/kernel/arch/mips32/src/asm.S@ dbd4ae5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since dbd4ae5 was d5042d28, checked in by Martin Decky <martin@…>, 16 years ago

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1/*
2 * Copyright (c) 2003 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/asm/regname.h>
30
31.text
32
33.macro cp0_read reg
34 mfc0 $2, \reg
35 j $31
36 nop
37.endm
38
39.macro cp0_write reg
40 mtc0 $4, \reg
41 j $31
42 nop
43.endm
44
45.set noat
46.set noreorder
47.set nomacro
48
49.global asm_delay_loop
50asm_delay_loop:
51 j $31
52 nop
53
54.global cpu_halt
55cpu_halt:
56 j cpu_halt
57 nop
58
59.global memsetb
60memsetb:
61 j _memsetb
62 nop
63
64.global memsetw
65memsetw:
66 j _memsetw
67 nop
68
69.global memcpy
70.global memcpy_from_uspace
71.global memcpy_to_uspace
72.global memcpy_from_uspace_failover_address
73.global memcpy_to_uspace_failover_address
74memcpy:
75memcpy_from_uspace:
76memcpy_to_uspace:
77 move $t2, $a0 /* save dst */
78
79 addiu $v0, $a1, 3
80 li $v1, -4 /* 0xfffffffffffffffc */
81 and $v0, $v0, $v1
82 beq $a1, $v0, 3f
83 move $t0, $a0
84
85 0:
86 beq $a2, $zero, 2f
87 move $a3, $zero
88
89 1:
90 addu $v0, $a1, $a3
91 lbu $a0, 0($v0)
92 addu $v1, $t0, $a3
93 addiu $a3, $a3, 1
94 bne $a3, $a2, 1b
95 sb $a0, 0($v1)
96
97 2:
98 jr $ra
99 move $v0, $t2
100
101 3:
102 addiu $v0, $a0, 3
103 and $v0, $v0, $v1
104 bne $a0, $v0, 0b
105 srl $t1, $a2, 2
106
107 beq $t1, $zero, 5f
108 move $a3, $zero
109
110 move $a3, $zero
111 move $a0, $zero
112
113 4:
114 addu $v0, $a1, $a0
115 lw $v1, 0($v0)
116 addiu $a3, $a3, 1
117 addu $v0, $t0, $a0
118 sw $v1, 0($v0)
119 bne $a3, $t1, 4b
120 addiu $a0, $a0, 4
121
122 5:
123 andi $a2, $a2, 0x3
124 beq $a2, $zero, 2b
125 nop
126
127 sll $v0, $a3, 2
128 addu $t1, $v0, $t0
129 move $a3, $zero
130 addu $t0, $v0, $a1
131
132 6:
133 addu $v0, $t0, $a3
134 lbu $a0, 0($v0)
135 addu $v1, $t1, $a3
136 addiu $a3, $a3, 1
137 bne $a3, $a2, 6b
138 sb $a0, 0($v1)
139
140 jr $ra
141 move $v0, $t2
142
143memcpy_from_uspace_failover_address:
144memcpy_to_uspace_failover_address:
145 jr $ra
146 move $v0, $zero
147
148.macro fpu_gp_save reg ctx
149 mfc1 $t0, $\reg
150 sw $t0, \reg * 4(\ctx)
151.endm
152
153.macro fpu_gp_restore reg ctx
154 lw $t0, \reg * 4(\ctx)
155 mtc1 $t0, $\reg
156.endm
157
158.macro fpu_ct_save reg ctx
159 cfc1 $t0, $1
160 sw $t0, (\reg + 32) * 4(\ctx)
161.endm
162
163.macro fpu_ct_restore reg ctx
164 lw $t0, (\reg + 32) * 4(\ctx)
165 ctc1 $t0, $\reg
166.endm
167
168.global fpu_context_save
169fpu_context_save:
170#ifdef CONFIG_FPU
171 fpu_gp_save 0, $a0
172 fpu_gp_save 1, $a0
173 fpu_gp_save 2, $a0
174 fpu_gp_save 3, $a0
175 fpu_gp_save 4, $a0
176 fpu_gp_save 5, $a0
177 fpu_gp_save 6, $a0
178 fpu_gp_save 7, $a0
179 fpu_gp_save 8, $a0
180 fpu_gp_save 9, $a0
181 fpu_gp_save 10, $a0
182 fpu_gp_save 11, $a0
183 fpu_gp_save 12, $a0
184 fpu_gp_save 13, $a0
185 fpu_gp_save 14, $a0
186 fpu_gp_save 15, $a0
187 fpu_gp_save 16, $a0
188 fpu_gp_save 17, $a0
189 fpu_gp_save 18, $a0
190 fpu_gp_save 19, $a0
191 fpu_gp_save 20, $a0
192 fpu_gp_save 21, $a0
193 fpu_gp_save 22, $a0
194 fpu_gp_save 23, $a0
195 fpu_gp_save 24, $a0
196 fpu_gp_save 25, $a0
197 fpu_gp_save 26, $a0
198 fpu_gp_save 27, $a0
199 fpu_gp_save 28, $a0
200 fpu_gp_save 29, $a0
201 fpu_gp_save 30, $a0
202 fpu_gp_save 31, $a0
203
204 fpu_ct_save 1, $a0
205 fpu_ct_save 2, $a0
206 fpu_ct_save 3, $a0
207 fpu_ct_save 4, $a0
208 fpu_ct_save 5, $a0
209 fpu_ct_save 6, $a0
210 fpu_ct_save 7, $a0
211 fpu_ct_save 8, $a0
212 fpu_ct_save 9, $a0
213 fpu_ct_save 10, $a0
214 fpu_ct_save 11, $a0
215 fpu_ct_save 12, $a0
216 fpu_ct_save 13, $a0
217 fpu_ct_save 14, $a0
218 fpu_ct_save 15, $a0
219 fpu_ct_save 16, $a0
220 fpu_ct_save 17, $a0
221 fpu_ct_save 18, $a0
222 fpu_ct_save 19, $a0
223 fpu_ct_save 20, $a0
224 fpu_ct_save 21, $a0
225 fpu_ct_save 22, $a0
226 fpu_ct_save 23, $a0
227 fpu_ct_save 24, $a0
228 fpu_ct_save 25, $a0
229 fpu_ct_save 26, $a0
230 fpu_ct_save 27, $a0
231 fpu_ct_save 28, $a0
232 fpu_ct_save 29, $a0
233 fpu_ct_save 30, $a0
234 fpu_ct_save 31, $a0
235#endif
236 j $ra
237 nop
238
239.global fpu_context_restore
240fpu_context_restore:
241#ifdef CONFIG_FPU
242 fpu_gp_restore 0, $a0
243 fpu_gp_restore 1, $a0
244 fpu_gp_restore 2, $a0
245 fpu_gp_restore 3, $a0
246 fpu_gp_restore 4, $a0
247 fpu_gp_restore 5, $a0
248 fpu_gp_restore 6, $a0
249 fpu_gp_restore 7, $a0
250 fpu_gp_restore 8, $a0
251 fpu_gp_restore 9, $a0
252 fpu_gp_restore 10, $a0
253 fpu_gp_restore 11, $a0
254 fpu_gp_restore 12, $a0
255 fpu_gp_restore 13, $a0
256 fpu_gp_restore 14, $a0
257 fpu_gp_restore 15, $a0
258 fpu_gp_restore 16, $a0
259 fpu_gp_restore 17, $a0
260 fpu_gp_restore 18, $a0
261 fpu_gp_restore 19, $a0
262 fpu_gp_restore 20, $a0
263 fpu_gp_restore 21, $a0
264 fpu_gp_restore 22, $a0
265 fpu_gp_restore 23, $a0
266 fpu_gp_restore 24, $a0
267 fpu_gp_restore 25, $a0
268 fpu_gp_restore 26, $a0
269 fpu_gp_restore 27, $a0
270 fpu_gp_restore 28, $a0
271 fpu_gp_restore 29, $a0
272 fpu_gp_restore 30, $a0
273 fpu_gp_restore 31, $a0
274
275 fpu_ct_restore 1, $a0
276 fpu_ct_restore 2, $a0
277 fpu_ct_restore 3, $a0
278 fpu_ct_restore 4, $a0
279 fpu_ct_restore 5, $a0
280 fpu_ct_restore 6, $a0
281 fpu_ct_restore 7, $a0
282 fpu_ct_restore 8, $a0
283 fpu_ct_restore 9, $a0
284 fpu_ct_restore 10, $a0
285 fpu_ct_restore 11, $a0
286 fpu_ct_restore 12, $a0
287 fpu_ct_restore 13, $a0
288 fpu_ct_restore 14, $a0
289 fpu_ct_restore 15, $a0
290 fpu_ct_restore 16, $a0
291 fpu_ct_restore 17, $a0
292 fpu_ct_restore 18, $a0
293 fpu_ct_restore 19, $a0
294 fpu_ct_restore 20, $a0
295 fpu_ct_restore 21, $a0
296 fpu_ct_restore 22, $a0
297 fpu_ct_restore 23, $a0
298 fpu_ct_restore 24, $a0
299 fpu_ct_restore 25, $a0
300 fpu_ct_restore 26, $a0
301 fpu_ct_restore 27, $a0
302 fpu_ct_restore 28, $a0
303 fpu_ct_restore 29, $a0
304 fpu_ct_restore 30, $a0
305 fpu_ct_restore 31, $a0
306#endif
307 j $ra
308 nop
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