source: mainline/kernel/arch/mips32/src/asm.S@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was b60c582, checked in by Martin Decky <martin@…>, 16 years ago

update for string changes
  • Property mode set to 100644
File size: 6.2 KB
Line 
1#
2# Copyright (c) 2003-2004 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/asm/regname.h>
30
31.text
32
33.macro cp0_read reg
34 mfc0 $2, \reg
35 j $31
36 nop
37.endm
38
39.macro cp0_write reg
40 mtc0 $4, \reg
41 j $31
42 nop
43.endm
44
45.set noat
46.set noreorder
47.set nomacro
48
49.global asm_delay_loop
50asm_delay_loop:
51 j $31
52 nop
53
54.global cpu_halt
55cpu_halt:
56 j cpu_halt
57 nop
58
59
60.global memsetb
61memsetb:
62 j _memsetb
63 nop
64
65
66.global memsetw
67memsetw:
68 j _memsetw
69 nop
70
71
72.global memcpy
73.global memcpy_from_uspace
74.global memcpy_to_uspace
75.global memcpy_from_uspace_failover_address
76.global memcpy_to_uspace_failover_address
77memcpy:
78memcpy_from_uspace:
79memcpy_to_uspace:
80 move $t2, $a0 # save dst
81
82 addiu $v0, $a1, 3
83 li $v1, -4 # 0xfffffffffffffffc
84 and $v0, $v0, $v1
85 beq $a1, $v0, 3f
86 move $t0, $a0
87
88 0:
89 beq $a2, $zero, 2f
90 move $a3, $zero
91
92 1:
93 addu $v0, $a1, $a3
94 lbu $a0, 0($v0)
95 addu $v1, $t0, $a3
96 addiu $a3, $a3, 1
97 bne $a3, $a2, 1b
98 sb $a0, 0($v1)
99
100 2:
101 jr $ra
102 move $v0, $t2
103
104 3:
105 addiu $v0, $a0, 3
106 and $v0, $v0, $v1
107 bne $a0, $v0, 0b
108 srl $t1, $a2, 2
109
110 beq $t1, $zero, 5f
111 move $a3, $zero
112
113 move $a3, $zero
114 move $a0, $zero
115
116 4:
117 addu $v0, $a1, $a0
118 lw $v1, 0($v0)
119 addiu $a3, $a3, 1
120 addu $v0, $t0, $a0
121 sw $v1, 0($v0)
122 bne $a3, $t1, 4b
123 addiu $a0, $a0, 4
124
125 5:
126 andi $a2, $a2, 0x3
127 beq $a2, $zero, 2b
128 nop
129
130 sll $v0, $a3, 2
131 addu $t1, $v0, $t0
132 move $a3, $zero
133 addu $t0, $v0, $a1
134
135 6:
136 addu $v0, $t0, $a3
137 lbu $a0, 0($v0)
138 addu $v1, $t1, $a3
139 addiu $a3, $a3, 1
140 bne $a3, $a2, 6b
141 sb $a0, 0($v1)
142
143 jr $ra
144 move $v0, $t2
145
146memcpy_from_uspace_failover_address:
147memcpy_to_uspace_failover_address:
148 jr $ra
149 move $v0, $zero
150
151
152
153.macro fpu_gp_save reg ctx
154 mfc1 $t0, $\reg
155 sw $t0, \reg * 4(\ctx)
156.endm
157
158.macro fpu_gp_restore reg ctx
159 lw $t0, \reg * 4(\ctx)
160 mtc1 $t0, $\reg
161.endm
162
163.macro fpu_ct_save reg ctx
164 cfc1 $t0, $1
165 sw $t0, (\reg + 32) * 4(\ctx)
166.endm
167
168.macro fpu_ct_restore reg ctx
169 lw $t0, (\reg + 32) * 4(\ctx)
170 ctc1 $t0, $\reg
171.endm
172
173
174.global fpu_context_save
175fpu_context_save:
176#ifdef CONFIG_FPU
177 fpu_gp_save 0, $a0
178 fpu_gp_save 1, $a0
179 fpu_gp_save 2, $a0
180 fpu_gp_save 3, $a0
181 fpu_gp_save 4, $a0
182 fpu_gp_save 5, $a0
183 fpu_gp_save 6, $a0
184 fpu_gp_save 7, $a0
185 fpu_gp_save 8, $a0
186 fpu_gp_save 9, $a0
187 fpu_gp_save 10, $a0
188 fpu_gp_save 11, $a0
189 fpu_gp_save 12, $a0
190 fpu_gp_save 13, $a0
191 fpu_gp_save 14, $a0
192 fpu_gp_save 15, $a0
193 fpu_gp_save 16, $a0
194 fpu_gp_save 17, $a0
195 fpu_gp_save 18, $a0
196 fpu_gp_save 19, $a0
197 fpu_gp_save 20, $a0
198 fpu_gp_save 21, $a0
199 fpu_gp_save 22, $a0
200 fpu_gp_save 23, $a0
201 fpu_gp_save 24, $a0
202 fpu_gp_save 25, $a0
203 fpu_gp_save 26, $a0
204 fpu_gp_save 27, $a0
205 fpu_gp_save 28, $a0
206 fpu_gp_save 29, $a0
207 fpu_gp_save 30, $a0
208 fpu_gp_save 31, $a0
209
210 fpu_ct_save 1, $a0
211 fpu_ct_save 2, $a0
212 fpu_ct_save 3, $a0
213 fpu_ct_save 4, $a0
214 fpu_ct_save 5, $a0
215 fpu_ct_save 6, $a0
216 fpu_ct_save 7, $a0
217 fpu_ct_save 8, $a0
218 fpu_ct_save 9, $a0
219 fpu_ct_save 10, $a0
220 fpu_ct_save 11, $a0
221 fpu_ct_save 12, $a0
222 fpu_ct_save 13, $a0
223 fpu_ct_save 14, $a0
224 fpu_ct_save 15, $a0
225 fpu_ct_save 16, $a0
226 fpu_ct_save 17, $a0
227 fpu_ct_save 18, $a0
228 fpu_ct_save 19, $a0
229 fpu_ct_save 20, $a0
230 fpu_ct_save 21, $a0
231 fpu_ct_save 22, $a0
232 fpu_ct_save 23, $a0
233 fpu_ct_save 24, $a0
234 fpu_ct_save 25, $a0
235 fpu_ct_save 26, $a0
236 fpu_ct_save 27, $a0
237 fpu_ct_save 28, $a0
238 fpu_ct_save 29, $a0
239 fpu_ct_save 30, $a0
240 fpu_ct_save 31, $a0
241#endif
242 j $ra
243 nop
244
245.global fpu_context_restore
246fpu_context_restore:
247#ifdef CONFIG_FPU
248 fpu_gp_restore 0, $a0
249 fpu_gp_restore 1, $a0
250 fpu_gp_restore 2, $a0
251 fpu_gp_restore 3, $a0
252 fpu_gp_restore 4, $a0
253 fpu_gp_restore 5, $a0
254 fpu_gp_restore 6, $a0
255 fpu_gp_restore 7, $a0
256 fpu_gp_restore 8, $a0
257 fpu_gp_restore 9, $a0
258 fpu_gp_restore 10, $a0
259 fpu_gp_restore 11, $a0
260 fpu_gp_restore 12, $a0
261 fpu_gp_restore 13, $a0
262 fpu_gp_restore 14, $a0
263 fpu_gp_restore 15, $a0
264 fpu_gp_restore 16, $a0
265 fpu_gp_restore 17, $a0
266 fpu_gp_restore 18, $a0
267 fpu_gp_restore 19, $a0
268 fpu_gp_restore 20, $a0
269 fpu_gp_restore 21, $a0
270 fpu_gp_restore 22, $a0
271 fpu_gp_restore 23, $a0
272 fpu_gp_restore 24, $a0
273 fpu_gp_restore 25, $a0
274 fpu_gp_restore 26, $a0
275 fpu_gp_restore 27, $a0
276 fpu_gp_restore 28, $a0
277 fpu_gp_restore 29, $a0
278 fpu_gp_restore 30, $a0
279 fpu_gp_restore 31, $a0
280
281 fpu_ct_restore 1, $a0
282 fpu_ct_restore 2, $a0
283 fpu_ct_restore 3, $a0
284 fpu_ct_restore 4, $a0
285 fpu_ct_restore 5, $a0
286 fpu_ct_restore 6, $a0
287 fpu_ct_restore 7, $a0
288 fpu_ct_restore 8, $a0
289 fpu_ct_restore 9, $a0
290 fpu_ct_restore 10, $a0
291 fpu_ct_restore 11, $a0
292 fpu_ct_restore 12, $a0
293 fpu_ct_restore 13, $a0
294 fpu_ct_restore 14, $a0
295 fpu_ct_restore 15, $a0
296 fpu_ct_restore 16, $a0
297 fpu_ct_restore 17, $a0
298 fpu_ct_restore 18, $a0
299 fpu_ct_restore 19, $a0
300 fpu_ct_restore 20, $a0
301 fpu_ct_restore 21, $a0
302 fpu_ct_restore 22, $a0
303 fpu_ct_restore 23, $a0
304 fpu_ct_restore 24, $a0
305 fpu_ct_restore 25, $a0
306 fpu_ct_restore 26, $a0
307 fpu_ct_restore 27, $a0
308 fpu_ct_restore 28, $a0
309 fpu_ct_restore 29, $a0
310 fpu_ct_restore 30, $a0
311 fpu_ct_restore 31, $a0
312#endif
313 j $ra
314 nop
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