source: mainline/kernel/arch/mips32/src/asm.S@ 26346bd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 26346bd was 26346bd, checked in by Martin Decky <martin@…>, 12 years ago

mips32: implement memset() and memcpy()
  • Property mode set to 100644
File size: 7.2 KB
RevLine 
[d5042d28]1/*
2 * Copyright (c) 2003 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[f761f1eb]28
[ffc277e]29#include <arch/asm/regname.h>
[7f341820]30
[f761f1eb]31.text
32
33.macro cp0_read reg
[56d5c7f]34 mfc0 $2, \reg
[4e1d008]35 j $31
36 nop
[f761f1eb]37.endm
38
39.macro cp0_write reg
[56d5c7f]40 mtc0 $4, \reg
[4e1d008]41 j $31
42 nop
[f761f1eb]43.endm
44
45.set noat
46.set noreorder
47.set nomacro
48
[7f341820]49.global asm_delay_loop
50asm_delay_loop:
51 j $31
52 nop
53
[f761f1eb]54.global cpu_halt
55cpu_halt:
56 j cpu_halt
57 nop
58
[26346bd]59.global memset
60.global memcpy
[e3c762cd]61.global memcpy_from_uspace
62.global memcpy_to_uspace
63.global memcpy_from_uspace_failover_address
64.global memcpy_to_uspace_failover_address
[26346bd]65
66memset:
67 move $v0, $a0
68 beqz $a2, 0f
69 addiu $t1, $a2, -1
70
71 negu $t0, $a0
72 andi $t0, $t0, 0x3
73 sltu $v1, $a2, $t0
74 bnez $v1, 1f
75 andi $a1, $a1, 0xff
76
77 7:
78 sltiu $v1, $a2, 4
79 beqz $v1, 2f
80 move $v1, $v0
81
82 move $t0, $a2
83
84 3:
85 sb $a1, 0($v1)
86 addiu $v1, $v1, 1
87 subu $a3, $v1, $v0
88 sltu $a3, $a3, $t0
89 bnez $a3, 3b
90 addiu $t1, $t1, -1
91
92 beq $a2, $t0, 0f
93 subu $a2, $a2, $t0
94
95 8:
96 srl $a0, $a2, 0x2
97 sll $t4, $a0, 0x2
98 beqz $t4, 4f
99 sll $t2, $a1, 0x10
100
101 sll $t3, $a1, 0x8
102 or $t3, $a1, $t3
103 sll $a3, $a1, 0x18
104 or $t3, $t3, $t2
105 or $t3, $t3, $a3
106 addu $t0, $v0, $t0
107 move $a3, $zero
108
109 5:
110 addiu $a3, $a3, 1
111 sltu $t2, $a3, $a0
112 sw $t3, 0($t0)
113 bnez $t2, 5b
114 addiu $t0, $t0, 4
115
116 addu $v1, $v1, $t4
117 beq $a2, $t4, 0f
118 subu $t1, $t1, $t4
119
120 4:
121 addiu $t1, $t1, 1
122 addu $t1, $v1, $t1
123 sb $a1, 0($v1)
124
125 6:
126 addiu $v1, $v1, 1
127 bnel $v1, $t1, 6b
128 sb $a1, 0($v1)
129
130 0:
131 jr $ra
132 nop
133
134 1:
135 j 7b
136 move $t0, $a2
137
138 2:
139 bnez $t0, 3b
140 nop
141
142 j 8b
143 subu $a2, $a2, $t0
144
145memcpy:
[e3c762cd]146memcpy_from_uspace:
147memcpy_to_uspace:
[d5042d28]148 move $t2, $a0 /* save dst */
[56d5c7f]149
150 addiu $v0, $a1, 3
[d5042d28]151 li $v1, -4 /* 0xfffffffffffffffc */
[56d5c7f]152 and $v0, $v0, $v1
153 beq $a1, $v0, 3f
154 move $t0, $a0
155
156 0:
157 beq $a2, $zero, 2f
158 move $a3, $zero
159
160 1:
161 addu $v0, $a1, $a3
162 lbu $a0, 0($v0)
163 addu $v1, $t0, $a3
164 addiu $a3, $a3, 1
165 bne $a3, $a2, 1b
166 sb $a0, 0($v1)
167
168 2:
169 jr $ra
170 move $v0, $t2
171
172 3:
173 addiu $v0, $a0, 3
174 and $v0, $v0, $v1
175 bne $a0, $v0, 0b
176 srl $t1, $a2, 2
177
178 beq $t1, $zero, 5f
179 move $a3, $zero
180
181 move $a3, $zero
182 move $a0, $zero
183
184 4:
185 addu $v0, $a1, $a0
186 lw $v1, 0($v0)
187 addiu $a3, $a3, 1
188 addu $v0, $t0, $a0
189 sw $v1, 0($v0)
190 bne $a3, $t1, 4b
191 addiu $a0, $a0, 4
192
193 5:
194 andi $a2, $a2, 0x3
195 beq $a2, $zero, 2b
196 nop
197
198 sll $v0, $a3, 2
199 addu $t1, $v0, $t0
200 move $a3, $zero
201 addu $t0, $v0, $a1
202
203 6:
204 addu $v0, $t0, $a3
205 lbu $a0, 0($v0)
206 addu $v1, $t1, $a3
207 addiu $a3, $a3, 1
208 bne $a3, $a2, 6b
209 sb $a0, 0($v1)
210
211 jr $ra
212 move $v0, $t2
[dcbc8be]213
[e3c762cd]214memcpy_from_uspace_failover_address:
215memcpy_to_uspace_failover_address:
[56d5c7f]216 jr $ra
217 move $v0, $zero
[e3c762cd]218
[ffc277e]219.macro fpu_gp_save reg ctx
[56d5c7f]220 mfc1 $t0, $\reg
221 sw $t0, \reg * 4(\ctx)
[ffc277e]222.endm
223
224.macro fpu_gp_restore reg ctx
[56d5c7f]225 lw $t0, \reg * 4(\ctx)
226 mtc1 $t0, $\reg
[ffc277e]227.endm
228
229.macro fpu_ct_save reg ctx
[56d5c7f]230 cfc1 $t0, $1
231 sw $t0, (\reg + 32) * 4(\ctx)
[d5042d28]232.endm
[ffc277e]233
234.macro fpu_ct_restore reg ctx
[56d5c7f]235 lw $t0, (\reg + 32) * 4(\ctx)
236 ctc1 $t0, $\reg
[ffc277e]237.endm
238
239.global fpu_context_save
240fpu_context_save:
[6da1013f]241#ifdef CONFIG_FPU
[56d5c7f]242 fpu_gp_save 0, $a0
243 fpu_gp_save 1, $a0
244 fpu_gp_save 2, $a0
245 fpu_gp_save 3, $a0
246 fpu_gp_save 4, $a0
247 fpu_gp_save 5, $a0
248 fpu_gp_save 6, $a0
249 fpu_gp_save 7, $a0
250 fpu_gp_save 8, $a0
251 fpu_gp_save 9, $a0
252 fpu_gp_save 10, $a0
253 fpu_gp_save 11, $a0
254 fpu_gp_save 12, $a0
255 fpu_gp_save 13, $a0
256 fpu_gp_save 14, $a0
257 fpu_gp_save 15, $a0
258 fpu_gp_save 16, $a0
259 fpu_gp_save 17, $a0
260 fpu_gp_save 18, $a0
261 fpu_gp_save 19, $a0
262 fpu_gp_save 20, $a0
263 fpu_gp_save 21, $a0
264 fpu_gp_save 22, $a0
265 fpu_gp_save 23, $a0
266 fpu_gp_save 24, $a0
267 fpu_gp_save 25, $a0
268 fpu_gp_save 26, $a0
269 fpu_gp_save 27, $a0
270 fpu_gp_save 28, $a0
271 fpu_gp_save 29, $a0
272 fpu_gp_save 30, $a0
273 fpu_gp_save 31, $a0
274
275 fpu_ct_save 1, $a0
276 fpu_ct_save 2, $a0
277 fpu_ct_save 3, $a0
278 fpu_ct_save 4, $a0
279 fpu_ct_save 5, $a0
280 fpu_ct_save 6, $a0
281 fpu_ct_save 7, $a0
282 fpu_ct_save 8, $a0
283 fpu_ct_save 9, $a0
284 fpu_ct_save 10, $a0
285 fpu_ct_save 11, $a0
286 fpu_ct_save 12, $a0
287 fpu_ct_save 13, $a0
288 fpu_ct_save 14, $a0
289 fpu_ct_save 15, $a0
290 fpu_ct_save 16, $a0
291 fpu_ct_save 17, $a0
292 fpu_ct_save 18, $a0
293 fpu_ct_save 19, $a0
294 fpu_ct_save 20, $a0
295 fpu_ct_save 21, $a0
296 fpu_ct_save 22, $a0
297 fpu_ct_save 23, $a0
298 fpu_ct_save 24, $a0
299 fpu_ct_save 25, $a0
300 fpu_ct_save 26, $a0
301 fpu_ct_save 27, $a0
302 fpu_ct_save 28, $a0
303 fpu_ct_save 29, $a0
304 fpu_ct_save 30, $a0
305 fpu_ct_save 31, $a0
306#endif
[ffc277e]307 j $ra
308 nop
309
310.global fpu_context_restore
311fpu_context_restore:
[6da1013f]312#ifdef CONFIG_FPU
[56d5c7f]313 fpu_gp_restore 0, $a0
314 fpu_gp_restore 1, $a0
315 fpu_gp_restore 2, $a0
316 fpu_gp_restore 3, $a0
317 fpu_gp_restore 4, $a0
318 fpu_gp_restore 5, $a0
319 fpu_gp_restore 6, $a0
320 fpu_gp_restore 7, $a0
321 fpu_gp_restore 8, $a0
322 fpu_gp_restore 9, $a0
323 fpu_gp_restore 10, $a0
324 fpu_gp_restore 11, $a0
325 fpu_gp_restore 12, $a0
326 fpu_gp_restore 13, $a0
327 fpu_gp_restore 14, $a0
328 fpu_gp_restore 15, $a0
329 fpu_gp_restore 16, $a0
330 fpu_gp_restore 17, $a0
331 fpu_gp_restore 18, $a0
332 fpu_gp_restore 19, $a0
333 fpu_gp_restore 20, $a0
334 fpu_gp_restore 21, $a0
335 fpu_gp_restore 22, $a0
336 fpu_gp_restore 23, $a0
337 fpu_gp_restore 24, $a0
338 fpu_gp_restore 25, $a0
339 fpu_gp_restore 26, $a0
340 fpu_gp_restore 27, $a0
341 fpu_gp_restore 28, $a0
342 fpu_gp_restore 29, $a0
343 fpu_gp_restore 30, $a0
344 fpu_gp_restore 31, $a0
345
346 fpu_ct_restore 1, $a0
347 fpu_ct_restore 2, $a0
348 fpu_ct_restore 3, $a0
349 fpu_ct_restore 4, $a0
350 fpu_ct_restore 5, $a0
351 fpu_ct_restore 6, $a0
352 fpu_ct_restore 7, $a0
353 fpu_ct_restore 8, $a0
354 fpu_ct_restore 9, $a0
355 fpu_ct_restore 10, $a0
356 fpu_ct_restore 11, $a0
357 fpu_ct_restore 12, $a0
358 fpu_ct_restore 13, $a0
359 fpu_ct_restore 14, $a0
360 fpu_ct_restore 15, $a0
361 fpu_ct_restore 16, $a0
362 fpu_ct_restore 17, $a0
363 fpu_ct_restore 18, $a0
364 fpu_ct_restore 19, $a0
365 fpu_ct_restore 20, $a0
366 fpu_ct_restore 21, $a0
367 fpu_ct_restore 22, $a0
368 fpu_ct_restore 23, $a0
369 fpu_ct_restore 24, $a0
370 fpu_ct_restore 25, $a0
371 fpu_ct_restore 26, $a0
372 fpu_ct_restore 27, $a0
373 fpu_ct_restore 28, $a0
374 fpu_ct_restore 29, $a0
375 fpu_ct_restore 30, $a0
376 fpu_ct_restore 31, $a0
377#endif
[ffc277e]378 j $ra
379 nop
[da52547]380
381.global early_putchar
382early_putchar:
383 j $ra
384 nop
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