source: mainline/kernel/arch/mips32/include/mm/tlb.h@ 06e1e95

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 06e1e95 was 06e1e95, checked in by Jakub Jermar <jakub@…>, 19 years ago

C99 compliant header guards (hopefully) everywhere in the kernel.
Formatting and indentation changes.
Small improvements in sparc64.

  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup mips32mm
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_mips32_TLB_H_
36#define KERN_mips32_TLB_H_
37
38#include <arch/exception.h>
39#include <typedefs.h>
40
41#ifdef TLBCNT
42# define TLB_ENTRY_COUNT TLBCNT
43#else
44# define TLB_ENTRY_COUNT 48
45#endif
46
47#define TLB_WIRED 1
48#define TLB_KSTACK_WIRED_INDEX 0
49
50#define TLB_PAGE_MASK_16K (0x3<<13)
51
52#define PAGE_UNCACHED 2
53#define PAGE_CACHEABLE_EXC_WRITE 5
54
55typedef union entry_lo entry_lo_t;
56typedef union entry_hi entry_hi_t;
57typedef union page_mask page_mask_t;
58typedef union index tlb_index_t;
59
60union entry_lo {
61 struct {
62#ifdef BIG_ENDIAN
63 unsigned : 2; /* zero */
64 unsigned pfn : 24; /* frame number */
65 unsigned c : 3; /* cache coherency attribute */
66 unsigned d : 1; /* dirty/write-protect bit */
67 unsigned v : 1; /* valid bit */
68 unsigned g : 1; /* global bit */
69#else
70 unsigned g : 1; /* global bit */
71 unsigned v : 1; /* valid bit */
72 unsigned d : 1; /* dirty/write-protect bit */
73 unsigned c : 3; /* cache coherency attribute */
74 unsigned pfn : 24; /* frame number */
75 unsigned : 2; /* zero */
76#endif
77 } __attribute__ ((packed));
78 uint32_t value;
79};
80
81/** Page Table Entry. */
82struct pte {
83 unsigned g : 1; /**< Global bit. */
84 unsigned p : 1; /**< Present bit. */
85 unsigned d : 1; /**< Dirty bit. */
86 unsigned cacheable : 1; /**< Cacheable bit. */
87 unsigned : 1; /**< Unused. */
88 unsigned soft_valid : 1; /**< Valid content even if not present. */
89 unsigned pfn : 24; /**< Physical frame number. */
90 unsigned w : 1; /**< Page writable bit. */
91 unsigned a : 1; /**< Accessed bit. */
92};
93
94union entry_hi {
95 struct {
96#ifdef BIG_ENDIAN
97 unsigned vpn2 : 19;
98 unsigned : 5;
99 unsigned asid : 8;
100#else
101 unsigned asid : 8;
102 unsigned : 5;
103 unsigned vpn2 : 19;
104#endif
105 } __attribute__ ((packed));
106 uint32_t value;
107};
108
109union page_mask {
110 struct {
111#ifdef BIG_ENDIAN
112 unsigned : 7;
113 unsigned mask : 12;
114 unsigned : 13;
115#else
116 unsigned : 13;
117 unsigned mask : 12;
118 unsigned : 7;
119#endif
120 } __attribute__ ((packed));
121 uint32_t value;
122};
123
124union index {
125 struct {
126#ifdef BIG_ENDIAN
127 unsigned p : 1;
128 unsigned : 27;
129 unsigned index : 4;
130#else
131 unsigned index : 4;
132 unsigned : 27;
133 unsigned p : 1;
134#endif
135 } __attribute__ ((packed));
136 uint32_t value;
137};
138
139/** Probe TLB for Matching Entry
140 *
141 * Probe TLB for Matching Entry.
142 */
143static inline void tlbp(void)
144{
145 __asm__ volatile ("tlbp\n\t");
146}
147
148
149/** Read Indexed TLB Entry
150 *
151 * Read Indexed TLB Entry.
152 */
153static inline void tlbr(void)
154{
155 __asm__ volatile ("tlbr\n\t");
156}
157
158/** Write Indexed TLB Entry
159 *
160 * Write Indexed TLB Entry.
161 */
162static inline void tlbwi(void)
163{
164 __asm__ volatile ("tlbwi\n\t");
165}
166
167/** Write Random TLB Entry
168 *
169 * Write Random TLB Entry.
170 */
171static inline void tlbwr(void)
172{
173 __asm__ volatile ("tlbwr\n\t");
174}
175
176#define tlb_invalidate(asid) tlb_invalidate_asid(asid)
177
178extern void tlb_invalid(istate_t *istate);
179extern void tlb_refill(istate_t *istate);
180extern void tlb_modified(istate_t *istate);
181
182#endif
183
184/** @}
185 */
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