source: mainline/kernel/arch/mips32/include/context_offset.h@ c7fbb90

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c7fbb90 was 7b213f2, checked in by Jakub Jermar <jakub@…>, 15 years ago

Rearrange mips32 istate_t to contain all registers and in a format suitable for syscalls / parameter passing. (Breaks mips32)

  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 * Copyright (c) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef KERN_mips32_CONTEXT_OFFSET_H_
30#define KERN_mips32_CONTEXT_OFFSET_H_
31
32#define OFFSET_SP 0x0
33#define OFFSET_PC 0x4
34#define OFFSET_S0 0x8
35#define OFFSET_S1 0xc
36#define OFFSET_S2 0x10
37#define OFFSET_S3 0x14
38#define OFFSET_S4 0x18
39#define OFFSET_S5 0x1c
40#define OFFSET_S6 0x20
41#define OFFSET_S7 0x24
42#define OFFSET_S8 0x28
43#define OFFSET_GP 0x2c
44
45#ifdef KERNEL
46# define OFFSET_IPL 0x30
47#else
48# define OFFSET_TLS 0x30
49
50# define OFFSET_F20 0x34
51# define OFFSET_F21 0x38
52# define OFFSET_F22 0x3c
53# define OFFSET_F23 0x40
54# define OFFSET_F24 0x44
55# define OFFSET_F25 0x48
56# define OFFSET_F26 0x4c
57# define OFFSET_F27 0x50
58# define OFFSET_F28 0x54
59# define OFFSET_F29 0x58
60# define OFFSET_F30 0x5c
61#endif /* KERNEL */
62
63#ifdef __ASM__
64
65#include <arch/asm/regname.h>
66
67# ctx: address of the structure with saved context
68.macro CONTEXT_SAVE_ARCH_CORE ctx:req
69 sw $s0,OFFSET_S0(\ctx)
70 sw $s1,OFFSET_S1(\ctx)
71 sw $s2,OFFSET_S2(\ctx)
72 sw $s3,OFFSET_S3(\ctx)
73 sw $s4,OFFSET_S4(\ctx)
74 sw $s5,OFFSET_S5(\ctx)
75 sw $s6,OFFSET_S6(\ctx)
76 sw $s7,OFFSET_S7(\ctx)
77 sw $s8,OFFSET_S8(\ctx)
78 sw $gp,OFFSET_GP(\ctx)
79
80#ifndef KERNEL
81 sw $k1,OFFSET_TLS(\ctx)
82
83#ifdef CONFIG_FPU
84 mfc1 $t0,$20
85 sw $t0, OFFSET_F20(\ctx)
86
87 mfc1 $t0,$21
88 sw $t0, OFFSET_F21(\ctx)
89
90 mfc1 $t0,$22
91 sw $t0, OFFSET_F22(\ctx)
92
93 mfc1 $t0,$23
94 sw $t0, OFFSET_F23(\ctx)
95
96 mfc1 $t0,$24
97 sw $t0, OFFSET_F24(\ctx)
98
99 mfc1 $t0,$25
100 sw $t0, OFFSET_F25(\ctx)
101
102 mfc1 $t0,$26
103 sw $t0, OFFSET_F26(\ctx)
104
105 mfc1 $t0,$27
106 sw $t0, OFFSET_F27(\ctx)
107
108 mfc1 $t0,$28
109 sw $t0, OFFSET_F28(\ctx)
110
111 mfc1 $t0,$29
112 sw $t0, OFFSET_F29(\ctx)
113
114 mfc1 $t0,$30
115 sw $t0, OFFSET_F30(\ctx)
116#endif /* CONFIG_FPU */
117#endif /* KERNEL */
118
119 sw $ra,OFFSET_PC(\ctx)
120 sw $sp,OFFSET_SP(\ctx)
121.endm
122
123# ctx: address of the structure with saved context
124.macro CONTEXT_RESTORE_ARCH_CORE ctx:req
125 lw $s0,OFFSET_S0(\ctx)
126 lw $s1,OFFSET_S1(\ctx)
127 lw $s2,OFFSET_S2(\ctx)
128 lw $s3,OFFSET_S3(\ctx)
129 lw $s4,OFFSET_S4(\ctx)
130 lw $s5,OFFSET_S5(\ctx)
131 lw $s6,OFFSET_S6(\ctx)
132 lw $s7,OFFSET_S7(\ctx)
133 lw $s8,OFFSET_S8(\ctx)
134 lw $gp,OFFSET_GP(\ctx)
135#ifndef KERNEL
136 lw $k1,OFFSET_TLS(\ctx)
137
138#ifdef CONFIG_FPU
139 lw $t0, OFFSET_F20(\ctx)
140 mtc1 $t0,$20
141
142 lw $t0, OFFSET_F21(\ctx)
143 mtc1 $t0,$21
144
145 lw $t0, OFFSET_F22(\ctx)
146 mtc1 $t0,$22
147
148 lw $t0, OFFSET_F23(\ctx)
149 mtc1 $t0,$23
150
151 lw $t0, OFFSET_F24(\ctx)
152 mtc1 $t0,$24
153
154 lw $t0, OFFSET_F25(\ctx)
155 mtc1 $t0,$25
156
157 lw $t0, OFFSET_F26(\ctx)
158 mtc1 $t0,$26
159
160 lw $t0, OFFSET_F27(\ctx)
161 mtc1 $t0,$27
162
163 lw $t0, OFFSET_F28(\ctx)
164 mtc1 $t0,$28
165
166 lw $t0, OFFSET_F29(\ctx)
167 mtc1 $t0,$29
168
169 lw $t0, OFFSET_F30(\ctx)
170 mtc1 $t0,$30
171#endif /* CONFIG_FPU */
172#endif /* KERNEL */
173
174 lw $ra,OFFSET_PC(\ctx)
175 lw $sp,OFFSET_SP(\ctx)
176.endm
177
178#endif
179
180
181#endif
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