source: mainline/kernel/arch/mips32/include/barrier.h@ d5087aa

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d5087aa was d5087aa, checked in by Jakub Jermar <jakub@…>, 17 years ago

Add smc_coherence_block().

  • Property mode set to 100644
File size: 2.0 KB
RevLine 
[7dd56f1]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
[7dd56f1]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[2f40fe4]29/** @addtogroup mips32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_mips32_BARRIER_H_
36#define KERN_mips32_BARRIER_H_
[7dd56f1]37
[511b45f]38/*
39 * TODO: implement true MIPS memory barriers for macros below.
40 */
[e7b7be3f]41#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")
42#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")
[7dd56f1]43
[e7b7be3f]44#define memory_barrier() asm volatile ("" ::: "memory")
45#define read_barrier() asm volatile ("" ::: "memory")
46#define write_barrier() asm volatile ("" ::: "memory")
[b52da8d7]47
[e25eca80]48#define smc_coherence(a)
[d5087aa]49#define smc_coherence_block(a, l)
[e25eca80]50
[7dd56f1]51#endif
[b45c443]52
[2f40fe4]53/** @}
[b45c443]54 */
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