source: mainline/kernel/arch/mips32/include/atomic.h@ 06e1e95

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 06e1e95 was 06e1e95, checked in by Jakub Jermar <jakub@…>, 19 years ago

C99 compliant header guards (hopefully) everywhere in the kernel.
Formatting and indentation changes.
Small improvements in sparc64.

  • Property mode set to 100644
File size: 2.4 KB
RevLine 
[f761f1eb]1/*
[b0bf501]2 * Copyright (C) 2005 Ondrej Palkovsky
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[2f40fe4]29/** @addtogroup mips32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_mips32_ATOMIC_H_
36#define KERN_mips32_ATOMIC_H_
[f761f1eb]37
[e507afa]38#define atomic_inc(x) ((void) atomic_add(x, 1))
39#define atomic_dec(x) ((void) atomic_add(x, -1))
[e3f41b6]40
[9a2d6e1]41#define atomic_postinc(x) (atomic_add(x, 1) - 1)
42#define atomic_postdec(x) (atomic_add(x, -1) + 1)
[73a4bab]43
[9a2d6e1]44#define atomic_preinc(x) atomic_add(x, 1)
45#define atomic_predec(x) atomic_add(x, -1)
[73a4bab]46
[e507afa]47/* Atomic addition of immediate value.
[e3f41b6]48 *
[e507afa]49 * @param val Memory location to which will be the immediate value added.
50 * @param i Signed immediate that will be added to *val.
[e3f41b6]51 *
[e507afa]52 * @return Value after addition.
[e3f41b6]53 */
[23684b7]54static inline long atomic_add(atomic_t *val, int i)
[e3f41b6]55{
[23684b7]56 long tmp, v;
[e3f41b6]57
[e507afa]58 __asm__ volatile (
[e3f41b6]59 "1:\n"
[e507afa]60 " ll %0, %1\n"
61 " addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */
62 " move %2, %0\n"
63 " sc %0, %1\n"
64 " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
[2f40fe4]65 " nop\n"
[80d2bdb]66 : "=r" (tmp), "=m" (val->count), "=r" (v)
[e507afa]67 : "i" (i), "i" (0)
[e3f41b6]68 );
[e507afa]69
70 return v;
[e3f41b6]71}
72
[f761f1eb]73#endif
[b45c443]74
[2f40fe4]75/** @}
[b45c443]76 */
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