| 1 | #
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| 2 | # Copyright (c) 2005 Jakub Jermar
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | #include <arch/register.h>
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| 30 | #include <arch/mm/page.h>
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| 31 | #include <arch/mm/asid.h>
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| 32 | #include <mm/asid.h>
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| 33 |
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| 34 | #define RR_MASK (0xFFFFFFFF00000002)
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| 35 | #define RID_SHIFT 8
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| 36 | #define PS_SHIFT 2
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| 37 |
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| 38 | #define KERNEL_TRANSLATION_I 0x0010000000000661
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| 39 | #define KERNEL_TRANSLATION_D 0x0010000000000661
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| 40 | #define KERNEL_TRANSLATION_VIO 0x0010000000000671
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| 41 | #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
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| 42 | #define KERNEL_TRANSLATION_FW 0x00100000F0000671
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| 43 |
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| 44 | .section K_TEXT_START, "ax"
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| 45 |
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| 46 | .global kernel_image_start
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| 47 |
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| 48 | stack0:
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| 49 | kernel_image_start:
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| 50 | .auto
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| 51 |
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| 52 | #ifdef CONFIG_SMP
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| 53 | # Identify self(CPU) in OS structures by ID / EID
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| 54 |
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| 55 | mov r9 = cr64
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| 56 | mov r10 = 1
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| 57 | movl r12 = 0xffffffff
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| 58 | movl r8 = cpu_by_id_eid_list
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| 59 | and r8 = r8, r12
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| 60 | shr r9 = r9, 16
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| 61 | add r8 = r8, r9
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| 62 | st1 [r8] = r10
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| 63 | #endif
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| 64 |
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| 65 | mov psr.l = r0
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| 66 | srlz.i
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| 67 | srlz.d
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| 68 |
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| 69 | # Fill TR.i and TR.d using Region Register #VRN_KERNEL
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| 70 |
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| 71 | movl r8 = (VRN_KERNEL << VRN_SHIFT)
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| 72 | mov r9 = rr[r8]
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| 73 |
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| 74 | movl r10 = (RR_MASK)
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| 75 | and r9 = r10, r9
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| 76 | movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
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| 77 | or r9 = r10, r9
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| 78 |
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| 79 | mov rr[r8] = r9
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| 80 |
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| 81 | movl r8 = (VRN_KERNEL << VRN_SHIFT)
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| 82 | mov cr.ifa = r8
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| 83 |
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| 84 | mov r11 = cr.itir
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| 85 | movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
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| 86 | or r10 = r10, r11
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| 87 | mov cr.itir = r10
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| 88 |
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| 89 | movl r10 = (KERNEL_TRANSLATION_I)
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| 90 | itr.i itr[r0] = r10
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| 91 | movl r10 = (KERNEL_TRANSLATION_D)
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| 92 | itr.d dtr[r0] = r10
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| 93 |
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| 94 | movl r7 = 1
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| 95 | movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
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| 96 | mov cr.ifa = r8
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| 97 | movl r10 = (KERNEL_TRANSLATION_VIO)
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| 98 | itr.d dtr[r7] = r10
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| 99 |
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| 100 | mov r11 = cr.itir
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| 101 | movl r10 = ~0xfc
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| 102 | and r10 = r10, r11
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| 103 | movl r11 = (IO_PAGE_WIDTH << PS_SHIFT)
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| 104 | or r10 = r10, r11
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| 105 | mov cr.itir = r10
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| 106 |
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| 107 | movl r7 = 2
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| 108 | movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
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| 109 | mov cr.ifa = r8
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| 110 | movl r10 = (KERNEL_TRANSLATION_IO)
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| 111 | itr.d dtr[r7] = r10
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| 112 |
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| 113 | # Setup mapping for fimware arrea (also SAPIC)
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| 114 |
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| 115 | mov r11 = cr.itir
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| 116 | movl r10 = ~0xfc
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| 117 | and r10 = r10, r11
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| 118 | movl r11 = (FW_PAGE_WIDTH << PS_SHIFT)
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| 119 | or r10 = r10, r11
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| 120 | mov cr.itir = r10
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| 121 |
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| 122 | movl r7 = 3
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| 123 | movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
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| 124 | mov cr.ifa = r8
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| 125 | movl r10 = (KERNEL_TRANSLATION_FW)
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| 126 | itr.d dtr[r7] = r10
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| 127 |
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| 128 | # Initialize PSR
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| 129 |
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| 130 | movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
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| 131 | mov r9 = psr
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| 132 |
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| 133 | or r10 = r10, r9
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| 134 | mov cr.ipsr = r10
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| 135 | mov cr.ifs = r0
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| 136 | movl r8 = paging_start
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| 137 | mov cr.iip = r8
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| 138 | srlz.d
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| 139 | srlz.i
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| 140 |
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| 141 | .explicit
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| 142 |
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| 143 | /*
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| 144 | * Return From Interrupt is the only way to
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| 145 | * fill the upper half word of PSR.
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| 146 | */
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| 147 | rfi ;;
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| 148 |
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| 149 |
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| 150 | .global paging_start
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| 151 | paging_start:
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| 152 |
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| 153 | /*
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| 154 | * Now we are paging.
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| 155 | */
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| 156 |
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| 157 | # Switch to register bank 1
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| 158 | bsw.1
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| 159 |
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| 160 | #ifdef CONFIG_SMP
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| 161 | # Am I BSP or AP?
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| 162 | movl r20 = bsp_started ;;
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| 163 | ld8 r20 = [r20] ;;
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| 164 | cmp.eq p3, p2 = r20, r0 ;;
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| 165 | #else
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| 166 | cmp.eq p3, p2 = r0, r0 ;; /* you are BSP */
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| 167 | #endif /* CONFIG_SMP */
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| 168 |
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| 169 | # Initialize register stack
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| 170 | mov ar.rsc = r0
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| 171 | movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
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| 172 | mov ar.bspstore = r8
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| 173 | loadrs
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| 174 |
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| 175 | # Initialize memory stack to some sane value
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| 176 | movl r12 = stack0 ;;
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| 177 | add r12 = -16, r12 /* allocate a scratch area on the stack */
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| 178 |
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| 179 | # Initialize gp (Global Pointer) register
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| 180 | movl r20 = (VRN_KERNEL << VRN_SHIFT);;
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| 181 | or r20 = r20,r1;;
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| 182 | movl r1 = _hardcoded_load_address
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| 183 |
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| 184 | /*
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| 185 | * Initialize hardcoded_* variables. Do only BSP
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| 186 | */
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| 187 | (p3) movl r14 = _hardcoded_ktext_size
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| 188 | (p3) movl r15 = _hardcoded_kdata_size
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| 189 | (p3) movl r16 = _hardcoded_load_address ;;
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| 190 | (p3) addl r17 = @gprel(hardcoded_ktext_size), gp
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| 191 | (p3) addl r18 = @gprel(hardcoded_kdata_size), gp
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| 192 | (p3) addl r19 = @gprel(hardcoded_load_address), gp
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| 193 | (p3) addl r21 = @gprel(bootinfo), gp
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| 194 | ;;
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| 195 | (p3) st8 [r17] = r14
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| 196 | (p3) st8 [r18] = r15
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| 197 | (p3) st8 [r19] = r16
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| 198 | (p3) st8 [r21] = r20
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| 199 |
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| 200 | ssm (1 << 19) ;; /* Disable f32 - f127 */
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| 201 | srlz.i
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| 202 | srlz.d ;;
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| 203 |
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| 204 | #ifdef CONFIG_SMP
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| 205 | (p2) movl r18 = main_ap ;;
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| 206 | (p2) mov b1 = r18 ;;
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| 207 | (p2) br.call.sptk.many b0 = b1
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| 208 |
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| 209 | # Mark that BSP is on
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| 210 | mov r20 = 1 ;;
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| 211 | movl r21 = bsp_started ;;
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| 212 | st8 [r21] = r20 ;;
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| 213 | #endif
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| 214 |
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| 215 | br.call.sptk.many b0 = arch_pre_main
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| 216 |
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| 217 | movl r18 = main_bsp ;;
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| 218 | mov b1 = r18 ;;
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| 219 | br.call.sptk.many b0 = b1
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| 220 |
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| 221 | 0:
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| 222 | br 0b
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| 223 |
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| 224 | #ifdef CONFIG_SMP
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| 225 |
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| 226 | .align 4096
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| 227 | kernel_image_ap_start:
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| 228 | .auto
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| 229 |
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| 230 | # Identify self(CPU) in OS structures by ID / EID
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| 231 |
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| 232 | mov r9 = cr64
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| 233 | mov r10 = 1
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| 234 | movl r12 = 0xffffffff
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| 235 | movl r8 = cpu_by_id_eid_list
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| 236 | and r8 = r8, r12
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| 237 | shr r9 = r9, 16
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| 238 | add r8 = r8, r9
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| 239 | st1 [r8] = r10
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| 240 |
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| 241 | # Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list)
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| 242 |
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| 243 | kernel_image_ap_start_loop:
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| 244 | movl r11 = kernel_image_ap_start_loop
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| 245 | and r11 = r11, r12
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| 246 | mov b1 = r11
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| 247 |
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| 248 | ld1 r20 = [r8] ;;
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| 249 | movl r21 = 3 ;;
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| 250 | cmp.eq p2, p3 = r20, r21 ;;
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| 251 | (p3) br.call.sptk.many b0 = b1
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| 252 |
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| 253 | movl r11 = kernel_image_start
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| 254 | and r11 = r11, r12
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| 255 | mov b1 = r11
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| 256 | br.call.sptk.many b0 = b1
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| 257 |
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| 258 | .align 16
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| 259 | .global bsp_started
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| 260 | bsp_started:
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| 261 | .space 8
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| 262 |
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| 263 | .align 4096
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| 264 | .global cpu_by_id_eid_list
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| 265 | cpu_by_id_eid_list:
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| 266 | .space 65536
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| 267 |
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| 268 | #endif /* CONFIG_SMP */
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