source: mainline/kernel/arch/ia64/src/start.S@ 9cc0d7c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9cc0d7c was 7a9364c, checked in by Jakub Vana <jakub.vana@…>, 18 years ago

Pack ski version of HelenOS to image.boot loader

  • Property mode set to 100644
File size: 3.7 KB
RevLine 
[30ef8ce]1#
[df4ed85]2# Copyright (c) 2005 Jakub Jermar
[30ef8ce]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[802bb95]29#include <arch/register.h>
[5ac2e61]30#include <arch/mm/page.h>
31#include <arch/mm/asid.h>
32#include <mm/asid.h>
33
34#define RR_MASK (0xFFFFFFFF00000002)
35#define RID_SHIFT 8
36#define PS_SHIFT 2
37
38#define KERNEL_TRANSLATION_I 0x0010000000000661
39#define KERNEL_TRANSLATION_D 0x0010000000000661
40
[9faddb3]41.section K_TEXT_START, "ax"
[00a44bc]42
[30ef8ce]43.global kernel_image_start
44
[2217ac3]45stack0:
[30ef8ce]46kernel_image_start:
[7f1bfce]47 .auto
[75eacab]48
[481c520]49 # Fill TR.i and TR.d using Region Register #VRN_KERNEL
[5ac2e61]50
[15819e37]51 movl r8 = (VRN_KERNEL << VRN_SHIFT)
52 mov r9 = rr[r8]
53 movl r10 = (RR_MASK)
54 and r9 = r10, r9
55 movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
56 or r9 = r10, r9
57 mov rr[r8] = r9
58
59 movl r8 = (VRN_KERNEL << VRN_SHIFT)
60 mov cr.ifa = r8
61 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
62 mov cr.itir = r10
63 movl r10 = (KERNEL_TRANSLATION_I)
64 itr.i itr[r0] = r10
65 movl r10 = (KERNEL_TRANSLATION_D)
66 itr.d dtr[r0] = r10
[5ac2e61]67
[7f1bfce]68 # initialize PSR
[75eacab]69 mov psr.l = r0
70 srlz.i
71 srlz.d
[15819e37]72 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
73 mov r9 = psr
74 or r10 = r10, r9
75 mov cr.ipsr = r10
76 mov cr.ifs = r0
77 movl r8 = paging_start
78 mov cr.iip = r8
[802bb95]79 srlz.d
[5ac2e61]80 srlz.i
[085434a]81
[481c520]82 .explicit
83 /*
84 * Return From Interupt is the only the way to fill upper half word of PSR.
85 */
86 rfi;;
[085434a]87
88.global paging_start
89paging_start:
[481c520]90
91 /*
92 * Now we are paging.
93 */
94
[802bb95]95 # switch to register bank 1
96 bsw.1
[7f1bfce]97
[c884ef1]98 # initialize register stack
[7f1bfce]99 mov ar.rsc = r0
[15819e37]100 movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
[5ac2e61]101 mov ar.bspstore = r8
[7f1bfce]102 loadrs
[2a0047fc]103
[c884ef1]104 # initialize memory stack to some sane value
[15819e37]105 movl r12 = stack0 ;;
[5ac2e61]106
[15819e37]107 add r12 = -16, r12 /* allocate a scratch area on the stack */
[00a44bc]108
[c884ef1]109 # initialize gp (Global Pointer) register
[7a9364c]110 movl r20 = (VRN_KERNEL << VRN_SHIFT);;
111 or r20 = r20,r1;;
[b994a60]112 movl r1 = _hardcoded_load_address
[7a9364c]113
[481c520]114 /*
115 * Initialize hardcoded_* variables.
116 */
[ac5d02b]117 movl r14 = _hardcoded_ktext_size
118 movl r15 = _hardcoded_kdata_size
[b994a60]119 movl r16 = _hardcoded_load_address ;;
[ac5d02b]120 addl r17 = @gprel(hardcoded_ktext_size), gp
121 addl r18 = @gprel(hardcoded_kdata_size), gp
122 addl r19 = @gprel(hardcoded_load_address), gp
[857c0e7]123 addl r21 = @gprel(bootinfo), gp
[ac5d02b]124 ;;
[ab46edb]125 st8 [r17] = r14
126 st8 [r18] = r15
[ac5d02b]127 st8 [r19] = r16
[857c0e7]128 st8 [r21] = r20
[5ac2e61]129
[15819e37]130 ssm (1 << 19) ;; /* Disable f32 - f127 */
131 srlz.i
132 srlz.d ;;
[41fa6f2]133
[6ecc8bce]134 br.call.sptk.many b0 = arch_pre_main
[41fa6f2]135
[15819e37]136 movl r18 = main_bsp ;;
137 mov b1 = r18 ;;
138 br.call.sptk.many b0 = b1
[5ac2e61]139
[41fa6f2]140
[2a0047fc]1410:
[47d78c6]142 br 0b
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