[30ef8ce] | 1 | #
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[df4ed85] | 2 | # Copyright (c) 2005 Jakub Jermar
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[30ef8ce] | 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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[802bb95] | 29 | #include <arch/register.h>
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[5ac2e61] | 30 | #include <arch/mm/page.h>
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| 31 | #include <arch/mm/asid.h>
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| 32 | #include <mm/asid.h>
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| 33 |
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| 34 | #define RR_MASK (0xFFFFFFFF00000002)
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| 35 | #define RID_SHIFT 8
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| 36 | #define PS_SHIFT 2
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| 37 |
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[7208b6c] | 38 | #define KERNEL_TRANSLATION_I 0x0010000000000661
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| 39 | #define KERNEL_TRANSLATION_D 0x0010000000000661
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| 40 | #define KERNEL_TRANSLATION_VIO 0x0010000000000671
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| 41 | #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
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| 42 | #define VIO_OFFSET 0x0002000000000000
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| 43 |
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| 44 | #define IO_OFFSET 0x0001000000000000
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| 45 |
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| 46 |
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[5ac2e61] | 47 |
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[9faddb3] | 48 | .section K_TEXT_START, "ax"
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[00a44bc] | 49 |
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[30ef8ce] | 50 | .global kernel_image_start
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| 51 |
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[2217ac3] | 52 | stack0:
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[30ef8ce] | 53 | kernel_image_start:
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[7f1bfce] | 54 | .auto
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[75eacab] | 55 |
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[7208b6c] | 56 | mov psr.l = r0
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| 57 | srlz.i
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| 58 | srlz.d
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| 59 |
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[481c520] | 60 | # Fill TR.i and TR.d using Region Register #VRN_KERNEL
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[5ac2e61] | 61 |
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[7208b6c] | 62 |
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[15819e37] | 63 | movl r8 = (VRN_KERNEL << VRN_SHIFT)
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| 64 | mov r9 = rr[r8]
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[7208b6c] | 65 |
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| 66 |
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[15819e37] | 67 | movl r10 = (RR_MASK)
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| 68 | and r9 = r10, r9
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| 69 | movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
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| 70 | or r9 = r10, r9
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[7208b6c] | 71 |
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| 72 |
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[15819e37] | 73 | mov rr[r8] = r9
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| 74 |
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[7208b6c] | 75 |
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| 76 |
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[15819e37] | 77 | movl r8 = (VRN_KERNEL << VRN_SHIFT)
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| 78 | mov cr.ifa = r8
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[7208b6c] | 79 |
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| 80 |
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| 81 | mov r11 = cr.itir ;;
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| 82 | movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
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| 83 | or r10 =r10 , r11 ;;
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| 84 | mov cr.itir = r10;;
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| 85 |
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| 86 |
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[15819e37] | 87 | movl r10 = (KERNEL_TRANSLATION_I)
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| 88 | itr.i itr[r0] = r10
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[7208b6c] | 89 |
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| 90 |
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[15819e37] | 91 | movl r10 = (KERNEL_TRANSLATION_D)
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| 92 | itr.d dtr[r0] = r10
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[5ac2e61] | 93 |
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[7208b6c] | 94 |
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| 95 | movl r7 = 1
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| 96 | movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
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| 97 | mov cr.ifa = r8
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| 98 | movl r10 = (KERNEL_TRANSLATION_VIO)
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| 99 | itr.d dtr[r7] = r10
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| 100 |
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| 101 |
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| 102 | mov r11 = cr.itir ;;
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| 103 | movl r10 = ~0xfc;;
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| 104 | and r10 =r10 , r11 ;;
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| 105 | movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
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| 106 | or r10 =r10 , r11 ;;
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| 107 | mov cr.itir = r10;;
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| 108 |
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| 109 |
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| 110 | movl r7 = 2
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| 111 | movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
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| 112 | mov cr.ifa = r8
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| 113 | movl r10 = (KERNEL_TRANSLATION_IO)
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| 114 | itr.d dtr[r7] = r10
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| 115 |
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| 116 |
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| 117 |
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| 118 |
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[7f1bfce] | 119 | # initialize PSR
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[15819e37] | 120 | movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
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| 121 | mov r9 = psr
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| 122 | or r10 = r10, r9
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| 123 | mov cr.ipsr = r10
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| 124 | mov cr.ifs = r0
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| 125 | movl r8 = paging_start
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| 126 | mov cr.iip = r8
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[802bb95] | 127 | srlz.d
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[5ac2e61] | 128 | srlz.i
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[085434a] | 129 |
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[481c520] | 130 | .explicit
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| 131 | /*
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| 132 | * Return From Interupt is the only the way to fill upper half word of PSR.
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| 133 | */
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| 134 | rfi;;
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[085434a] | 135 |
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| 136 | .global paging_start
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| 137 | paging_start:
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[481c520] | 138 |
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| 139 | /*
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| 140 | * Now we are paging.
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| 141 | */
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| 142 |
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[802bb95] | 143 | # switch to register bank 1
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| 144 | bsw.1
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[7f1bfce] | 145 |
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[c884ef1] | 146 | # initialize register stack
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[7f1bfce] | 147 | mov ar.rsc = r0
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[15819e37] | 148 | movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
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[5ac2e61] | 149 | mov ar.bspstore = r8
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[7f1bfce] | 150 | loadrs
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[2a0047fc] | 151 |
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[c884ef1] | 152 | # initialize memory stack to some sane value
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[15819e37] | 153 | movl r12 = stack0 ;;
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[5ac2e61] | 154 |
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[15819e37] | 155 | add r12 = -16, r12 /* allocate a scratch area on the stack */
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[00a44bc] | 156 |
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[c884ef1] | 157 | # initialize gp (Global Pointer) register
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[7a9364c] | 158 | movl r20 = (VRN_KERNEL << VRN_SHIFT);;
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| 159 | or r20 = r20,r1;;
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[b994a60] | 160 | movl r1 = _hardcoded_load_address
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[7a9364c] | 161 |
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[481c520] | 162 | /*
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| 163 | * Initialize hardcoded_* variables.
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| 164 | */
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[ac5d02b] | 165 | movl r14 = _hardcoded_ktext_size
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| 166 | movl r15 = _hardcoded_kdata_size
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[b994a60] | 167 | movl r16 = _hardcoded_load_address ;;
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[ac5d02b] | 168 | addl r17 = @gprel(hardcoded_ktext_size), gp
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| 169 | addl r18 = @gprel(hardcoded_kdata_size), gp
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| 170 | addl r19 = @gprel(hardcoded_load_address), gp
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[857c0e7] | 171 | addl r21 = @gprel(bootinfo), gp
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[ac5d02b] | 172 | ;;
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[ab46edb] | 173 | st8 [r17] = r14
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| 174 | st8 [r18] = r15
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[ac5d02b] | 175 | st8 [r19] = r16
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[857c0e7] | 176 | st8 [r21] = r20
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[5ac2e61] | 177 |
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[15819e37] | 178 | ssm (1 << 19) ;; /* Disable f32 - f127 */
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| 179 | srlz.i
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| 180 | srlz.d ;;
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[41fa6f2] | 181 |
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[6ecc8bce] | 182 | br.call.sptk.many b0 = arch_pre_main
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[41fa6f2] | 183 |
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[15819e37] | 184 | movl r18 = main_bsp ;;
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| 185 | mov b1 = r18 ;;
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| 186 | br.call.sptk.many b0 = b1
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[5ac2e61] | 187 |
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[41fa6f2] | 188 |
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[2a0047fc] | 189 | 0:
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[47d78c6] | 190 | br 0b
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