source: mainline/kernel/arch/ia64/src/start.S@ 8ccd2ea

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8ccd2ea was 7208b6c, checked in by Jakub Vana <jakub.vana@…>, 17 years ago

Basic IA64 boot and kernel suport for real machines

  • Property mode set to 100644
File size: 4.3 KB
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[30ef8ce]1#
[df4ed85]2# Copyright (c) 2005 Jakub Jermar
[30ef8ce]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[802bb95]29#include <arch/register.h>
[5ac2e61]30#include <arch/mm/page.h>
31#include <arch/mm/asid.h>
32#include <mm/asid.h>
33
34#define RR_MASK (0xFFFFFFFF00000002)
35#define RID_SHIFT 8
36#define PS_SHIFT 2
37
[7208b6c]38#define KERNEL_TRANSLATION_I 0x0010000000000661
39#define KERNEL_TRANSLATION_D 0x0010000000000661
40#define KERNEL_TRANSLATION_VIO 0x0010000000000671
41#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
42#define VIO_OFFSET 0x0002000000000000
43
44#define IO_OFFSET 0x0001000000000000
45
46
[5ac2e61]47
[9faddb3]48.section K_TEXT_START, "ax"
[00a44bc]49
[30ef8ce]50.global kernel_image_start
51
[2217ac3]52stack0:
[30ef8ce]53kernel_image_start:
[7f1bfce]54 .auto
[75eacab]55
[7208b6c]56 mov psr.l = r0
57 srlz.i
58 srlz.d
59
[481c520]60 # Fill TR.i and TR.d using Region Register #VRN_KERNEL
[5ac2e61]61
[7208b6c]62
[15819e37]63 movl r8 = (VRN_KERNEL << VRN_SHIFT)
64 mov r9 = rr[r8]
[7208b6c]65
66
[15819e37]67 movl r10 = (RR_MASK)
68 and r9 = r10, r9
69 movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
70 or r9 = r10, r9
[7208b6c]71
72
[15819e37]73 mov rr[r8] = r9
74
[7208b6c]75
76
[15819e37]77 movl r8 = (VRN_KERNEL << VRN_SHIFT)
78 mov cr.ifa = r8
[7208b6c]79
80
81 mov r11 = cr.itir ;;
82 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
83 or r10 =r10 , r11 ;;
84 mov cr.itir = r10;;
85
86
[15819e37]87 movl r10 = (KERNEL_TRANSLATION_I)
88 itr.i itr[r0] = r10
[7208b6c]89
90
[15819e37]91 movl r10 = (KERNEL_TRANSLATION_D)
92 itr.d dtr[r0] = r10
[5ac2e61]93
[7208b6c]94
95 movl r7 = 1
96 movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
97 mov cr.ifa = r8
98 movl r10 = (KERNEL_TRANSLATION_VIO)
99 itr.d dtr[r7] = r10
100
101
102 mov r11 = cr.itir ;;
103 movl r10 = ~0xfc;;
104 and r10 =r10 , r11 ;;
105 movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
106 or r10 =r10 , r11 ;;
107 mov cr.itir = r10;;
108
109
110 movl r7 = 2
111 movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
112 mov cr.ifa = r8
113 movl r10 = (KERNEL_TRANSLATION_IO)
114 itr.d dtr[r7] = r10
115
116
117
118
[7f1bfce]119 # initialize PSR
[15819e37]120 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
121 mov r9 = psr
122 or r10 = r10, r9
123 mov cr.ipsr = r10
124 mov cr.ifs = r0
125 movl r8 = paging_start
126 mov cr.iip = r8
[802bb95]127 srlz.d
[5ac2e61]128 srlz.i
[085434a]129
[481c520]130 .explicit
131 /*
132 * Return From Interupt is the only the way to fill upper half word of PSR.
133 */
134 rfi;;
[085434a]135
136.global paging_start
137paging_start:
[481c520]138
139 /*
140 * Now we are paging.
141 */
142
[802bb95]143 # switch to register bank 1
144 bsw.1
[7f1bfce]145
[c884ef1]146 # initialize register stack
[7f1bfce]147 mov ar.rsc = r0
[15819e37]148 movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
[5ac2e61]149 mov ar.bspstore = r8
[7f1bfce]150 loadrs
[2a0047fc]151
[c884ef1]152 # initialize memory stack to some sane value
[15819e37]153 movl r12 = stack0 ;;
[5ac2e61]154
[15819e37]155 add r12 = -16, r12 /* allocate a scratch area on the stack */
[00a44bc]156
[c884ef1]157 # initialize gp (Global Pointer) register
[7a9364c]158 movl r20 = (VRN_KERNEL << VRN_SHIFT);;
159 or r20 = r20,r1;;
[b994a60]160 movl r1 = _hardcoded_load_address
[7a9364c]161
[481c520]162 /*
163 * Initialize hardcoded_* variables.
164 */
[ac5d02b]165 movl r14 = _hardcoded_ktext_size
166 movl r15 = _hardcoded_kdata_size
[b994a60]167 movl r16 = _hardcoded_load_address ;;
[ac5d02b]168 addl r17 = @gprel(hardcoded_ktext_size), gp
169 addl r18 = @gprel(hardcoded_kdata_size), gp
170 addl r19 = @gprel(hardcoded_load_address), gp
[857c0e7]171 addl r21 = @gprel(bootinfo), gp
[ac5d02b]172 ;;
[ab46edb]173 st8 [r17] = r14
174 st8 [r18] = r15
[ac5d02b]175 st8 [r19] = r16
[857c0e7]176 st8 [r21] = r20
[5ac2e61]177
[15819e37]178 ssm (1 << 19) ;; /* Disable f32 - f127 */
179 srlz.i
180 srlz.d ;;
[41fa6f2]181
[6ecc8bce]182 br.call.sptk.many b0 = arch_pre_main
[41fa6f2]183
[15819e37]184 movl r18 = main_bsp ;;
185 mov b1 = r18 ;;
186 br.call.sptk.many b0 = b1
[5ac2e61]187
[41fa6f2]188
[2a0047fc]1890:
[47d78c6]190 br 0b
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