source: mainline/kernel/arch/ia64/src/start.S@ 7510326

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7510326 was 36df4109, checked in by Jakub Jermar <jakub@…>, 9 years ago

Introduce architecure-specific operations

This replaces the arch_*_init() functions with an arch_ops_t structure
defined for each architecture. Undefined operations are treated as NOPs.

  • Property mode set to 100644
File size: 3.8 KB
RevLine 
[30ef8ce]1#
[df4ed85]2# Copyright (c) 2005 Jakub Jermar
[30ef8ce]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[27f67f5]29#include <abi/asmtool.h>
[802bb95]30#include <arch/register.h>
[5ac2e61]31#include <arch/mm/page.h>
32#include <arch/mm/asid.h>
33#include <mm/asid.h>
34
[5bda2f3e]35#define RR_MASK (0xFFFFFFFF00000002)
36#define RID_SHIFT 8
37#define PS_SHIFT 2
[7208b6c]38
[5bda2f3e]39#define KERNEL_TRANSLATION_I 0x0010000000000661
40#define KERNEL_TRANSLATION_D 0x0010000000000661
[5ac2e61]41
[9faddb3]42.section K_TEXT_START, "ax"
[00a44bc]43
[2217ac3]44stack0:
[fe7abd0]45
46#
47# Kernel entry point.
48#
49# This is where we are passed control from the boot code.
50# Register contents:
51#
52# r2 Address of the boot code's bootinfo structure.
53#
[27f67f5]54SYMBOL(kernel_image_start)
[7f1bfce]55 .auto
[5bda2f3e]56
[7208b6c]57 mov psr.l = r0
58 srlz.i
59 srlz.d
[5bda2f3e]60
[481c520]61 # Fill TR.i and TR.d using Region Register #VRN_KERNEL
[5bda2f3e]62
[15819e37]63 movl r8 = (VRN_KERNEL << VRN_SHIFT)
64 mov r9 = rr[r8]
[5bda2f3e]65
[15819e37]66 movl r10 = (RR_MASK)
67 and r9 = r10, r9
[d9ee2ea]68 movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
[5bda2f3e]69 or r9 = r10, r9
70
[15819e37]71 mov rr[r8] = r9
[5bda2f3e]72
[15819e37]73 movl r8 = (VRN_KERNEL << VRN_SHIFT)
74 mov cr.ifa = r8
[5bda2f3e]75
[acee917]76 mov r11 = cr.itir
77 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
78 or r10 = r10, r11
79 mov cr.itir = r10
[5bda2f3e]80
[15819e37]81 movl r10 = (KERNEL_TRANSLATION_I)
82 itr.i itr[r0] = r10
83 movl r10 = (KERNEL_TRANSLATION_D)
84 itr.d dtr[r0] = r10
[5bda2f3e]85
[22f0561]86 # Initialize DCR
[93d66ef]87
88 movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
89 mov r9 = cr.dcr
90 or r10 = r10, r9
91 mov cr.dcr = r10
92
[666773c]93 # Initialize PSR
[5bda2f3e]94
[15819e37]95 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
96 mov r9 = psr
[5bda2f3e]97
[15819e37]98 or r10 = r10, r9
99 mov cr.ipsr = r10
100 mov cr.ifs = r0
101 movl r8 = paging_start
102 mov cr.iip = r8
[802bb95]103 srlz.d
[5ac2e61]104 srlz.i
[5bda2f3e]105
[481c520]106 .explicit
[5bda2f3e]107
[481c520]108 /*
[0e56eb1a]109 * Return From Interrupt is the only way to
110 * fill the upper half word of PSR.
[481c520]111 */
[acee917]112 rfi ;;
[085434a]113
114paging_start:
[5bda2f3e]115
[481c520]116 /*
117 * Now we are paging.
118 */
[d75628da]119
120 #
121 # Set Interruption Vector Address
122 # (i.e. location of interruption vector table)
123 #
124 movl r8 = ivt ;;
125 mov cr.iva = r8
126 srlz.d ;;
127
[5bda2f3e]128
[666773c]129 # Switch to register bank 1
[802bb95]130 bsw.1
[5bda2f3e]131
[666773c]132 # Initialize register stack
[7f1bfce]133 mov ar.rsc = r0
[15819e37]134 movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
[5ac2e61]135 mov ar.bspstore = r8
[7f1bfce]136 loadrs
[972c60ce]137
[7f0e7b6]138 #
[d75628da]139 # Initialize memory stack to some sane value and allocate a scratch area
[7f0e7b6]140 # on it.
141 #
142 movl sp = stack0 ;;
143 add sp = -16, sp
[5bda2f3e]144
[666773c]145 # Initialize gp (Global Pointer) register
[18ba2e4f]146 movl gp = __gp
[7a9364c]147
[18ba2e4f]148 #
[fe7abd0]149 # Initialize bootinfo on BSP.
150 #
151 movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;
152 or r20 = r20, r2 ;;
[e5c1186]153 addl r21 = @gprel(bootinfo), gp ;;
154 st8 [r21] = r20
[5bda2f3e]155
[15819e37]156 ssm (1 << 19) ;; /* Disable f32 - f127 */
157 srlz.i
158 srlz.d ;;
[972c60ce]159
[36df4109]160 br.call.sptk.many b0 = ia64_pre_main
[fae1647]1610:
162 br.call.sptk.many b0 = main_bsp
[2a0047fc]1630:
[47d78c6]164 br 0b
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