| [30ef8ce] | 1 | #
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| [df4ed85] | 2 | # Copyright (c) 2005 Jakub Jermar
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| [30ef8ce] | 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| [802bb95] | 29 | #include <arch/register.h>
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| [5ac2e61] | 30 | #include <arch/mm/page.h>
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| 31 | #include <arch/mm/asid.h>
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| 32 | #include <mm/asid.h>
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| 33 |
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| [5bda2f3e] | 34 | #define RR_MASK (0xFFFFFFFF00000002)
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| 35 | #define RID_SHIFT 8
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| 36 | #define PS_SHIFT 2
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| [7208b6c] | 37 |
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| [5bda2f3e] | 38 | #define KERNEL_TRANSLATION_I 0x0010000000000661
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| 39 | #define KERNEL_TRANSLATION_D 0x0010000000000661
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| [5ac2e61] | 40 |
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| [9faddb3] | 41 | .section K_TEXT_START, "ax"
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| [00a44bc] | 42 |
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| [30ef8ce] | 43 | .global kernel_image_start
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| 44 |
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| [2217ac3] | 45 | stack0:
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| [fe7abd0] | 46 |
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| 47 | #
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| 48 | # Kernel entry point.
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| 49 | #
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| 50 | # This is where we are passed control from the boot code.
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| 51 | # Register contents:
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| 52 | #
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| 53 | # r2 Address of the boot code's bootinfo structure.
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| 54 | #
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| [30ef8ce] | 55 | kernel_image_start:
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| [7f1bfce] | 56 | .auto
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| [5bda2f3e] | 57 |
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| [7208b6c] | 58 | mov psr.l = r0
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| 59 | srlz.i
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| 60 | srlz.d
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| [5bda2f3e] | 61 |
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| [481c520] | 62 | # Fill TR.i and TR.d using Region Register #VRN_KERNEL
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| [5bda2f3e] | 63 |
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| [15819e37] | 64 | movl r8 = (VRN_KERNEL << VRN_SHIFT)
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| 65 | mov r9 = rr[r8]
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| [5bda2f3e] | 66 |
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| [15819e37] | 67 | movl r10 = (RR_MASK)
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| 68 | and r9 = r10, r9
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| [d9ee2ea] | 69 | movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
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| [5bda2f3e] | 70 | or r9 = r10, r9
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| 71 |
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| [15819e37] | 72 | mov rr[r8] = r9
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| [5bda2f3e] | 73 |
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| [15819e37] | 74 | movl r8 = (VRN_KERNEL << VRN_SHIFT)
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| 75 | mov cr.ifa = r8
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| [5bda2f3e] | 76 |
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| [acee917] | 77 | mov r11 = cr.itir
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| 78 | movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
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| 79 | or r10 = r10, r11
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| 80 | mov cr.itir = r10
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| [5bda2f3e] | 81 |
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| [15819e37] | 82 | movl r10 = (KERNEL_TRANSLATION_I)
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| 83 | itr.i itr[r0] = r10
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| 84 | movl r10 = (KERNEL_TRANSLATION_D)
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| 85 | itr.d dtr[r0] = r10
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| [5bda2f3e] | 86 |
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| [22f0561] | 87 | # Initialize DCR
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| [93d66ef] | 88 |
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| 89 | movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
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| 90 | mov r9 = cr.dcr
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| 91 | or r10 = r10, r9
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| 92 | mov cr.dcr = r10
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| 93 |
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| [666773c] | 94 | # Initialize PSR
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| [5bda2f3e] | 95 |
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| [15819e37] | 96 | movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
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| 97 | mov r9 = psr
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| [5bda2f3e] | 98 |
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| [15819e37] | 99 | or r10 = r10, r9
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| 100 | mov cr.ipsr = r10
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| 101 | mov cr.ifs = r0
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| 102 | movl r8 = paging_start
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| 103 | mov cr.iip = r8
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| [802bb95] | 104 | srlz.d
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| [5ac2e61] | 105 | srlz.i
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| [5bda2f3e] | 106 |
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| [481c520] | 107 | .explicit
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| [5bda2f3e] | 108 |
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| [481c520] | 109 | /*
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| [0e56eb1a] | 110 | * Return From Interrupt is the only way to
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| 111 | * fill the upper half word of PSR.
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| [481c520] | 112 | */
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| [acee917] | 113 | rfi ;;
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| [085434a] | 114 |
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| 115 | .global paging_start
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| 116 | paging_start:
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| [5bda2f3e] | 117 |
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| [481c520] | 118 | /*
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| 119 | * Now we are paging.
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| 120 | */
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| [d75628da] | 121 |
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| 122 | #
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| 123 | # Set Interruption Vector Address
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| 124 | # (i.e. location of interruption vector table)
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| 125 | #
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| 126 | movl r8 = ivt ;;
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| 127 | mov cr.iva = r8
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| 128 | srlz.d ;;
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| 129 |
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| [5bda2f3e] | 130 |
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| [666773c] | 131 | # Switch to register bank 1
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| [802bb95] | 132 | bsw.1
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| [5bda2f3e] | 133 |
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| [666773c] | 134 | # Initialize register stack
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| [7f1bfce] | 135 | mov ar.rsc = r0
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| [15819e37] | 136 | movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
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| [5ac2e61] | 137 | mov ar.bspstore = r8
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| [7f1bfce] | 138 | loadrs
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| [972c60ce] | 139 |
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| [7f0e7b6] | 140 | #
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| [d75628da] | 141 | # Initialize memory stack to some sane value and allocate a scratch area
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| [7f0e7b6] | 142 | # on it.
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| 143 | #
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| 144 | movl sp = stack0 ;;
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| 145 | add sp = -16, sp
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| [5bda2f3e] | 146 |
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| [666773c] | 147 | # Initialize gp (Global Pointer) register
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| [18ba2e4f] | 148 | movl gp = __gp
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| [7a9364c] | 149 |
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| [18ba2e4f] | 150 | #
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| [fe7abd0] | 151 | # Initialize bootinfo on BSP.
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| 152 | #
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| 153 | movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;
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| 154 | or r20 = r20, r2 ;;
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| [e5c1186] | 155 | addl r21 = @gprel(bootinfo), gp ;;
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| 156 | st8 [r21] = r20
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| [5bda2f3e] | 157 |
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| [15819e37] | 158 | ssm (1 << 19) ;; /* Disable f32 - f127 */
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| 159 | srlz.i
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| 160 | srlz.d ;;
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| [972c60ce] | 161 |
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| [6ecc8bce] | 162 | br.call.sptk.many b0 = arch_pre_main
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| [fae1647] | 163 | 0:
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| 164 | br.call.sptk.many b0 = main_bsp
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| [2a0047fc] | 165 | 0:
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| [47d78c6] | 166 | br 0b
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