1 | /*
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2 | * Copyright (c) 2006 Jakub Jermar
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** @addtogroup ia64mm
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30 | * @{
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31 | */
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32 | /** @file
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33 | */
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34 |
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35 | /*
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36 | * TLB management.
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37 | */
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38 |
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39 | #include <mm/tlb.h>
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40 | #include <mm/asid.h>
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41 | #include <mm/page.h>
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42 | #include <mm/as.h>
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43 | #include <arch/mm/tlb.h>
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44 | #include <arch/mm/page.h>
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45 | #include <arch/mm/vhpt.h>
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46 | #include <arch/barrier.h>
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47 | #include <arch/interrupt.h>
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48 | #include <arch/pal/pal.h>
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49 | #include <arch/asm.h>
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50 | #include <panic.h>
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51 | #include <print.h>
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52 | #include <arch.h>
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53 | #include <interrupt.h>
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54 |
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55 | /** Invalidate all TLB entries. */
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56 | void tlb_invalidate_all(void)
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57 | {
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58 | ipl_t ipl;
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59 | uintptr_t adr;
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60 | uint32_t count1, count2, stride1, stride2;
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61 |
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62 | unsigned int i, j;
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63 |
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64 | adr = PAL_PTCE_INFO_BASE();
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65 | count1 = PAL_PTCE_INFO_COUNT1();
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66 | count2 = PAL_PTCE_INFO_COUNT2();
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67 | stride1 = PAL_PTCE_INFO_STRIDE1();
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68 | stride2 = PAL_PTCE_INFO_STRIDE2();
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69 |
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70 | ipl = interrupts_disable();
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71 |
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72 | for (i = 0; i < count1; i++) {
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73 | for (j = 0; j < count2; j++) {
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74 | asm volatile (
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75 | "ptc.e %0 ;;"
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76 | :
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77 | : "r" (adr)
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78 | );
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79 | adr += stride2;
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80 | }
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81 | adr += stride1;
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82 | }
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83 |
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84 | interrupts_restore(ipl);
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85 |
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86 | srlz_d();
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87 | srlz_i();
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88 | #ifdef CONFIG_VHPT
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89 | vhpt_invalidate_all();
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90 | #endif
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91 | }
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92 |
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93 | /** Invalidate entries belonging to an address space.
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94 | *
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95 | * @param asid Address space identifier.
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96 | */
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97 | void tlb_invalidate_asid(asid_t asid)
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98 | {
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99 | tlb_invalidate_all();
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100 | }
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101 |
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102 |
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103 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
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104 | {
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105 | region_register rr;
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106 | bool restore_rr = false;
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107 | int b = 0;
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108 | int c = cnt;
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109 |
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110 | uintptr_t va;
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111 | va = page;
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112 |
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113 | rr.word = rr_read(VA2VRN(va));
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114 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
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115 | /*
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116 | * The selected region register does not contain required RID.
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117 | * Save the old content of the register and replace the RID.
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118 | */
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119 | region_register rr0;
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120 |
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121 | rr0 = rr;
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122 | rr0.map.rid = ASID2RID(asid, VA2VRN(va));
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123 | rr_write(VA2VRN(va), rr0.word);
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124 | srlz_d();
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125 | srlz_i();
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126 | }
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127 |
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128 | while(c >>= 1)
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129 | b++;
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130 | b >>= 1;
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131 | uint64_t ps;
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132 |
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133 | switch (b) {
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134 | case 0: /* cnt 1 - 3 */
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135 | ps = PAGE_WIDTH;
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136 | break;
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137 | case 1: /* cnt 4 - 15 */
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138 | ps = PAGE_WIDTH + 2;
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139 | va &= ~((1 << ps) - 1);
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140 | break;
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141 | case 2: /* cnt 16 - 63 */
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142 | ps = PAGE_WIDTH + 4;
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143 | va &= ~((1 << ps) - 1);
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144 | break;
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145 | case 3: /* cnt 64 - 255 */
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146 | ps = PAGE_WIDTH + 6;
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147 | va &= ~((1 << ps) - 1);
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148 | break;
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149 | case 4: /* cnt 256 - 1023 */
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150 | ps = PAGE_WIDTH + 8;
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151 | va &= ~((1 << ps) - 1);
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152 | break;
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153 | case 5: /* cnt 1024 - 4095 */
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154 | ps = PAGE_WIDTH + 10;
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155 | va &= ~((1 << ps) - 1);
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156 | break;
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157 | case 6: /* cnt 4096 - 16383 */
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158 | ps = PAGE_WIDTH + 12;
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159 | va &= ~((1 << ps) - 1);
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160 | break;
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161 | case 7: /* cnt 16384 - 65535 */
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162 | case 8: /* cnt 65536 - (256K - 1) */
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163 | ps = PAGE_WIDTH + 14;
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164 | va &= ~((1 << ps) - 1);
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165 | break;
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166 | default:
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167 | ps = PAGE_WIDTH + 18;
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168 | va &= ~((1 << ps) - 1);
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169 | break;
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170 | }
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171 | for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
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172 | asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2));
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173 | srlz_d();
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174 | srlz_i();
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175 |
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176 | if (restore_rr) {
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177 | rr_write(VA2VRN(va), rr.word);
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178 | srlz_d();
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179 | srlz_i();
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180 | }
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181 | }
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182 |
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183 | /** Insert data into data translation cache.
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184 | *
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185 | * @param va Virtual page address.
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186 | * @param asid Address space identifier.
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187 | * @param entry The rest of TLB entry as required by TLB insertion
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188 | * format.
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189 | */
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190 | void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
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191 | {
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192 | tc_mapping_insert(va, asid, entry, true);
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193 | }
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194 |
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195 | /** Insert data into instruction translation cache.
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196 | *
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197 | * @param va Virtual page address.
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198 | * @param asid Address space identifier.
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199 | * @param entry The rest of TLB entry as required by TLB insertion
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200 | * format.
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201 | */
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202 | void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
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203 | {
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204 | tc_mapping_insert(va, asid, entry, false);
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205 | }
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206 |
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207 | /** Insert data into instruction or data translation cache.
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208 | *
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209 | * @param va Virtual page address.
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210 | * @param asid Address space identifier.
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211 | * @param entry The rest of TLB entry as required by TLB insertion
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212 | * format.
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213 | * @param dtc If true, insert into data translation cache, use
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214 | * instruction translation cache otherwise.
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215 | */
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216 | void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
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217 | {
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218 | region_register rr;
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219 | bool restore_rr = false;
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220 |
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221 | rr.word = rr_read(VA2VRN(va));
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222 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
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223 | /*
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224 | * The selected region register does not contain required RID.
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225 | * Save the old content of the register and replace the RID.
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226 | */
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227 | region_register rr0;
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228 |
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229 | rr0 = rr;
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230 | rr0.map.rid = ASID2RID(asid, VA2VRN(va));
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231 | rr_write(VA2VRN(va), rr0.word);
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232 | srlz_d();
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233 | srlz_i();
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234 | }
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235 |
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236 | asm volatile (
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237 | "mov r8 = psr;;\n"
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238 | "rsm %0;;\n" /* PSR_IC_MASK */
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239 | "srlz.d;;\n"
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240 | "srlz.i;;\n"
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241 | "mov cr.ifa = %1\n" /* va */
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242 | "mov cr.itir = %2;;\n" /* entry.word[1] */
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243 | "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */
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244 | "(p6) itc.i %3;;\n"
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245 | "(p7) itc.d %3;;\n"
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246 | "mov psr.l = r8;;\n"
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247 | "srlz.d;;\n"
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248 | :
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249 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
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250 | "r" (entry.word[0]), "r" (dtc)
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251 | : "p6", "p7", "r8"
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252 | );
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253 |
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254 | if (restore_rr) {
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255 | rr_write(VA2VRN(va), rr.word);
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256 | srlz_d();
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257 | srlz_i();
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258 | }
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259 | }
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260 |
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261 | /** Insert data into instruction translation register.
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262 | *
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263 | * @param va Virtual page address.
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264 | * @param asid Address space identifier.
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265 | * @param entry The rest of TLB entry as required by TLB insertion
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266 | * format.
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267 | * @param tr Translation register.
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268 | */
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269 | void
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270 | itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
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271 | {
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272 | tr_mapping_insert(va, asid, entry, false, tr);
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273 | }
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274 |
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275 | /** Insert data into data translation register.
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276 | *
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277 | * @param va Virtual page address.
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278 | * @param asid Address space identifier.
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279 | * @param entry The rest of TLB entry as required by TLB insertion
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280 | * format.
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281 | * @param tr Translation register.
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282 | */
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283 | void
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284 | dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
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285 | {
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286 | tr_mapping_insert(va, asid, entry, true, tr);
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287 | }
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288 |
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289 | /** Insert data into instruction or data translation register.
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290 | *
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291 | * @param va Virtual page address.
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292 | * @param asid Address space identifier.
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293 | * @param entry The rest of TLB entry as required by TLB insertion
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294 | * format.
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295 | * @param dtr If true, insert into data translation register, use
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296 | * instruction translation register otherwise.
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297 | * @param tr Translation register.
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298 | */
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299 | void
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300 | tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
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301 | size_t tr)
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302 | {
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303 | region_register rr;
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304 | bool restore_rr = false;
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305 |
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306 | rr.word = rr_read(VA2VRN(va));
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307 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
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308 | /*
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309 | * The selected region register does not contain required RID.
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310 | * Save the old content of the register and replace the RID.
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311 | */
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312 | region_register rr0;
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313 |
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314 | rr0 = rr;
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315 | rr0.map.rid = ASID2RID(asid, VA2VRN(va));
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316 | rr_write(VA2VRN(va), rr0.word);
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317 | srlz_d();
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318 | srlz_i();
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319 | }
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320 |
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321 | asm volatile (
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322 | "mov r8 = psr;;\n"
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323 | "rsm %0;;\n" /* PSR_IC_MASK */
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324 | "srlz.d;;\n"
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325 | "srlz.i;;\n"
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326 | "mov cr.ifa = %1\n" /* va */
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327 | "mov cr.itir = %2;;\n" /* entry.word[1] */
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328 | "cmp.eq p6,p7 = %5,r0;;\n" /* decide between itr and dtr */
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329 | "(p6) itr.i itr[%4] = %3;;\n"
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330 | "(p7) itr.d dtr[%4] = %3;;\n"
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331 | "mov psr.l = r8;;\n"
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332 | "srlz.d;;\n"
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333 | :
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334 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
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335 | "r" (entry.word[0]), "r" (tr), "r" (dtr)
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336 | : "p6", "p7", "r8"
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337 | );
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338 |
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339 | if (restore_rr) {
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340 | rr_write(VA2VRN(va), rr.word);
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341 | srlz_d();
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342 | srlz_i();
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343 | }
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344 | }
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345 |
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346 | /** Insert data into DTLB.
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347 | *
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348 | * @param page Virtual page address including VRN bits.
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349 | * @param frame Physical frame address.
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350 | * @param dtr If true, insert into data translation register, use data
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351 | * translation cache otherwise.
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352 | * @param tr Translation register if dtr is true, ignored otherwise.
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353 | */
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354 | void
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355 | dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
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356 | size_t tr)
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357 | {
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358 | tlb_entry_t entry;
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359 |
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360 | entry.word[0] = 0;
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361 | entry.word[1] = 0;
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362 |
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363 | entry.p = true; /* present */
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364 | entry.ma = MA_WRITEBACK;
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365 | entry.a = true; /* already accessed */
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366 | entry.d = true; /* already dirty */
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367 | entry.pl = PL_KERNEL;
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368 | entry.ar = AR_READ | AR_WRITE;
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369 | entry.ppn = frame >> PPN_SHIFT;
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370 | entry.ps = PAGE_WIDTH;
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371 |
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372 | if (dtr)
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373 | dtr_mapping_insert(page, ASID_KERNEL, entry, tr);
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374 | else
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375 | dtc_mapping_insert(page, ASID_KERNEL, entry);
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376 | }
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377 |
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378 | /** Purge kernel entries from DTR.
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379 | *
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380 | * Purge DTR entries used by the kernel.
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381 | *
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382 | * @param page Virtual page address including VRN bits.
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383 | * @param width Width of the purge in bits.
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384 | */
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385 | void dtr_purge(uintptr_t page, size_t width)
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386 | {
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387 | asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
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388 | }
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389 |
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390 |
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391 | /** Copy content of PTE into data translation cache.
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392 | *
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393 | * @param t PTE.
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394 | */
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395 | void dtc_pte_copy(pte_t *t)
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396 | {
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397 | tlb_entry_t entry;
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398 |
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399 | entry.word[0] = 0;
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400 | entry.word[1] = 0;
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401 |
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402 | entry.p = t->p;
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403 | entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
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404 | entry.a = t->a;
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405 | entry.d = t->d;
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406 | entry.pl = t->k ? PL_KERNEL : PL_USER;
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407 | entry.ar = t->w ? AR_WRITE : AR_READ;
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408 | entry.ppn = t->frame >> PPN_SHIFT;
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409 | entry.ps = PAGE_WIDTH;
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410 |
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411 | dtc_mapping_insert(t->page, t->as->asid, entry);
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412 | #ifdef CONFIG_VHPT
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413 | vhpt_mapping_insert(t->page, t->as->asid, entry);
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414 | #endif
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415 | }
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416 |
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417 | /** Copy content of PTE into instruction translation cache.
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418 | *
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419 | * @param t PTE.
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420 | */
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421 | void itc_pte_copy(pte_t *t)
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422 | {
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423 | tlb_entry_t entry;
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424 |
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425 | entry.word[0] = 0;
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426 | entry.word[1] = 0;
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427 |
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428 | ASSERT(t->x);
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429 |
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430 | entry.p = t->p;
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431 | entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
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432 | entry.a = t->a;
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433 | entry.pl = t->k ? PL_KERNEL : PL_USER;
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434 | entry.ar = t->x ? (AR_EXECUTE | AR_READ) : AR_READ;
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435 | entry.ppn = t->frame >> PPN_SHIFT;
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436 | entry.ps = PAGE_WIDTH;
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437 |
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438 | itc_mapping_insert(t->page, t->as->asid, entry);
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439 | #ifdef CONFIG_VHPT
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440 | vhpt_mapping_insert(t->page, t->as->asid, entry);
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441 | #endif
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442 | }
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443 |
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444 | /** Instruction TLB fault handler for faults with VHPT turned off.
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445 | *
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446 | * @param vector Interruption vector.
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447 | * @param istate Structure with saved interruption state.
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448 | */
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449 | void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
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450 | {
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451 | region_register rr;
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452 | rid_t rid;
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453 | uintptr_t va;
|
---|
454 | pte_t *t;
|
---|
455 |
|
---|
456 | va = istate->cr_ifa; /* faulting address */
|
---|
457 | rr.word = rr_read(VA2VRN(va));
|
---|
458 | rid = rr.map.rid;
|
---|
459 |
|
---|
460 | page_table_lock(AS, true);
|
---|
461 | t = page_mapping_find(AS, va);
|
---|
462 | if (t) {
|
---|
463 | /*
|
---|
464 | * The mapping was found in software page hash table.
|
---|
465 | * Insert it into data translation cache.
|
---|
466 | */
|
---|
467 | itc_pte_copy(t);
|
---|
468 | page_table_unlock(AS, true);
|
---|
469 | } else {
|
---|
470 | /*
|
---|
471 | * Forward the page fault to address space page fault handler.
|
---|
472 | */
|
---|
473 | page_table_unlock(AS, true);
|
---|
474 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
|
---|
475 | fault_if_from_uspace(istate,"Page fault at %p.",va);
|
---|
476 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
|
---|
477 | istate->cr_iip);
|
---|
478 | }
|
---|
479 | }
|
---|
480 | }
|
---|
481 |
|
---|
482 | static int is_io_page_accessible(int page)
|
---|
483 | {
|
---|
484 | if (TASK->arch.iomap)
|
---|
485 | return bitmap_get(TASK->arch.iomap, page);
|
---|
486 | else
|
---|
487 | return 0;
|
---|
488 | }
|
---|
489 |
|
---|
490 | #define IO_FRAME_BASE 0xFFFFC000000
|
---|
491 |
|
---|
492 | /**
|
---|
493 | * There is special handling of memory mapped legacy io, because of 4KB sized
|
---|
494 | * access for userspace.
|
---|
495 | *
|
---|
496 | * @param va Virtual address of page fault.
|
---|
497 | * @param istate Structure with saved interruption state.
|
---|
498 | *
|
---|
499 | * @return One on success, zero on failure.
|
---|
500 | */
|
---|
501 | static int try_memmap_io_insertion(uintptr_t va, istate_t *istate)
|
---|
502 | {
|
---|
503 | if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) {
|
---|
504 | if (TASK) {
|
---|
505 | uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >>
|
---|
506 | USPACE_IO_PAGE_WIDTH;
|
---|
507 |
|
---|
508 | if (is_io_page_accessible(io_page)) {
|
---|
509 | uint64_t page, frame;
|
---|
510 |
|
---|
511 | page = IO_OFFSET +
|
---|
512 | (1 << USPACE_IO_PAGE_WIDTH) * io_page;
|
---|
513 | frame = IO_FRAME_BASE +
|
---|
514 | (1 << USPACE_IO_PAGE_WIDTH) * io_page;
|
---|
515 |
|
---|
516 | tlb_entry_t entry;
|
---|
517 |
|
---|
518 | entry.word[0] = 0;
|
---|
519 | entry.word[1] = 0;
|
---|
520 |
|
---|
521 | entry.p = true; /* present */
|
---|
522 | entry.ma = MA_UNCACHEABLE;
|
---|
523 | entry.a = true; /* already accessed */
|
---|
524 | entry.d = true; /* already dirty */
|
---|
525 | entry.pl = PL_USER;
|
---|
526 | entry.ar = AR_READ | AR_WRITE;
|
---|
527 | entry.ppn = frame >> PPN_SHIFT;
|
---|
528 | entry.ps = USPACE_IO_PAGE_WIDTH;
|
---|
529 |
|
---|
530 | dtc_mapping_insert(page, TASK->as->asid, entry);
|
---|
531 | return 1;
|
---|
532 | } else {
|
---|
533 | fault_if_from_uspace(istate,
|
---|
534 | "IO access fault at %p.", va);
|
---|
535 | }
|
---|
536 | }
|
---|
537 | }
|
---|
538 |
|
---|
539 | return 0;
|
---|
540 | }
|
---|
541 |
|
---|
542 | /** Data TLB fault handler for faults with VHPT turned off.
|
---|
543 | *
|
---|
544 | * @param vector Interruption vector.
|
---|
545 | * @param istate Structure with saved interruption state.
|
---|
546 | */
|
---|
547 | void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
|
---|
548 | {
|
---|
549 | region_register rr;
|
---|
550 | rid_t rid;
|
---|
551 | uintptr_t va;
|
---|
552 | pte_t *t;
|
---|
553 |
|
---|
554 | va = istate->cr_ifa; /* faulting address */
|
---|
555 | rr.word = rr_read(VA2VRN(va));
|
---|
556 | rid = rr.map.rid;
|
---|
557 | if (RID2ASID(rid) == ASID_KERNEL) {
|
---|
558 | if (VA2VRN(va) == VRN_KERNEL) {
|
---|
559 | /*
|
---|
560 | * Provide KA2PA(identity) mapping for faulting piece of
|
---|
561 | * kernel address space.
|
---|
562 | */
|
---|
563 | dtlb_kernel_mapping_insert(va, KA2PA(va), false, 0);
|
---|
564 | return;
|
---|
565 | }
|
---|
566 | }
|
---|
567 |
|
---|
568 | page_table_lock(AS, true);
|
---|
569 | t = page_mapping_find(AS, va);
|
---|
570 | if (t) {
|
---|
571 | /*
|
---|
572 | * The mapping was found in the software page hash table.
|
---|
573 | * Insert it into data translation cache.
|
---|
574 | */
|
---|
575 | dtc_pte_copy(t);
|
---|
576 | page_table_unlock(AS, true);
|
---|
577 | } else {
|
---|
578 | page_table_unlock(AS, true);
|
---|
579 | if (try_memmap_io_insertion(va, istate))
|
---|
580 | return;
|
---|
581 | /*
|
---|
582 | * Forward the page fault to the address space page fault
|
---|
583 | * handler.
|
---|
584 | */
|
---|
585 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
|
---|
586 | fault_if_from_uspace(istate,"Page fault at %p.",va);
|
---|
587 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
|
---|
588 | istate->cr_iip);
|
---|
589 | }
|
---|
590 | }
|
---|
591 | }
|
---|
592 |
|
---|
593 | /** Data nested TLB fault handler.
|
---|
594 | *
|
---|
595 | * This fault should not occur.
|
---|
596 | *
|
---|
597 | * @param vector Interruption vector.
|
---|
598 | * @param istate Structure with saved interruption state.
|
---|
599 | */
|
---|
600 | void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
|
---|
601 | {
|
---|
602 | panic("%s.", __func__);
|
---|
603 | }
|
---|
604 |
|
---|
605 | /** Data Dirty bit fault handler.
|
---|
606 | *
|
---|
607 | * @param vector Interruption vector.
|
---|
608 | * @param istate Structure with saved interruption state.
|
---|
609 | */
|
---|
610 | void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
|
---|
611 | {
|
---|
612 | region_register rr;
|
---|
613 | rid_t rid;
|
---|
614 | uintptr_t va;
|
---|
615 | pte_t *t;
|
---|
616 |
|
---|
617 | va = istate->cr_ifa; /* faulting address */
|
---|
618 | rr.word = rr_read(VA2VRN(va));
|
---|
619 | rid = rr.map.rid;
|
---|
620 |
|
---|
621 | page_table_lock(AS, true);
|
---|
622 | t = page_mapping_find(AS, va);
|
---|
623 | ASSERT(t && t->p);
|
---|
624 | if (t && t->p && t->w) {
|
---|
625 | /*
|
---|
626 | * Update the Dirty bit in page tables and reinsert
|
---|
627 | * the mapping into DTC.
|
---|
628 | */
|
---|
629 | t->d = true;
|
---|
630 | dtc_pte_copy(t);
|
---|
631 | } else {
|
---|
632 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
|
---|
633 | fault_if_from_uspace(istate,"Page fault at %p.",va);
|
---|
634 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
|
---|
635 | istate->cr_iip);
|
---|
636 | }
|
---|
637 | }
|
---|
638 | page_table_unlock(AS, true);
|
---|
639 | }
|
---|
640 |
|
---|
641 | /** Instruction access bit fault handler.
|
---|
642 | *
|
---|
643 | * @param vector Interruption vector.
|
---|
644 | * @param istate Structure with saved interruption state.
|
---|
645 | */
|
---|
646 | void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
|
---|
647 | {
|
---|
648 | region_register rr;
|
---|
649 | rid_t rid;
|
---|
650 | uintptr_t va;
|
---|
651 | pte_t *t;
|
---|
652 |
|
---|
653 | va = istate->cr_ifa; /* faulting address */
|
---|
654 | rr.word = rr_read(VA2VRN(va));
|
---|
655 | rid = rr.map.rid;
|
---|
656 |
|
---|
657 | page_table_lock(AS, true);
|
---|
658 | t = page_mapping_find(AS, va);
|
---|
659 | ASSERT(t && t->p);
|
---|
660 | if (t && t->p && t->x) {
|
---|
661 | /*
|
---|
662 | * Update the Accessed bit in page tables and reinsert
|
---|
663 | * the mapping into ITC.
|
---|
664 | */
|
---|
665 | t->a = true;
|
---|
666 | itc_pte_copy(t);
|
---|
667 | } else {
|
---|
668 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
|
---|
669 | fault_if_from_uspace(istate, "Page fault at %p.", va);
|
---|
670 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
|
---|
671 | istate->cr_iip);
|
---|
672 | }
|
---|
673 | }
|
---|
674 | page_table_unlock(AS, true);
|
---|
675 | }
|
---|
676 |
|
---|
677 | /** Data access bit fault handler.
|
---|
678 | *
|
---|
679 | * @param vector Interruption vector.
|
---|
680 | * @param istate Structure with saved interruption state.
|
---|
681 | */
|
---|
682 | void data_access_bit_fault(uint64_t vector, istate_t *istate)
|
---|
683 | {
|
---|
684 | region_register rr;
|
---|
685 | rid_t rid;
|
---|
686 | uintptr_t va;
|
---|
687 | pte_t *t;
|
---|
688 |
|
---|
689 | va = istate->cr_ifa; /* faulting address */
|
---|
690 | rr.word = rr_read(VA2VRN(va));
|
---|
691 | rid = rr.map.rid;
|
---|
692 |
|
---|
693 | page_table_lock(AS, true);
|
---|
694 | t = page_mapping_find(AS, va);
|
---|
695 | ASSERT(t && t->p);
|
---|
696 | if (t && t->p) {
|
---|
697 | /*
|
---|
698 | * Update the Accessed bit in page tables and reinsert
|
---|
699 | * the mapping into DTC.
|
---|
700 | */
|
---|
701 | t->a = true;
|
---|
702 | dtc_pte_copy(t);
|
---|
703 | } else {
|
---|
704 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
|
---|
705 | fault_if_from_uspace(istate, "Page fault at %p.", va);
|
---|
706 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
|
---|
707 | istate->cr_iip);
|
---|
708 | }
|
---|
709 | }
|
---|
710 | page_table_unlock(AS, true);
|
---|
711 | }
|
---|
712 |
|
---|
713 | /** Page not present fault handler.
|
---|
714 | *
|
---|
715 | * @param vector Interruption vector.
|
---|
716 | * @param istate Structure with saved interruption state.
|
---|
717 | */
|
---|
718 | void page_not_present(uint64_t vector, istate_t *istate)
|
---|
719 | {
|
---|
720 | region_register rr;
|
---|
721 | rid_t rid;
|
---|
722 | uintptr_t va;
|
---|
723 | pte_t *t;
|
---|
724 |
|
---|
725 | va = istate->cr_ifa; /* faulting address */
|
---|
726 | rr.word = rr_read(VA2VRN(va));
|
---|
727 | rid = rr.map.rid;
|
---|
728 |
|
---|
729 | page_table_lock(AS, true);
|
---|
730 | t = page_mapping_find(AS, va);
|
---|
731 | ASSERT(t);
|
---|
732 |
|
---|
733 | if (t->p) {
|
---|
734 | /*
|
---|
735 | * If the Present bit is set in page hash table, just copy it
|
---|
736 | * and update ITC/DTC.
|
---|
737 | */
|
---|
738 | if (t->x)
|
---|
739 | itc_pte_copy(t);
|
---|
740 | else
|
---|
741 | dtc_pte_copy(t);
|
---|
742 | page_table_unlock(AS, true);
|
---|
743 | } else {
|
---|
744 | page_table_unlock(AS, true);
|
---|
745 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
|
---|
746 | fault_if_from_uspace(istate, "Page fault at %p.", va);
|
---|
747 | panic("%s: va=%p, rid=%d.", __func__, va, rid);
|
---|
748 | }
|
---|
749 | }
|
---|
750 | }
|
---|
751 |
|
---|
752 | void tlb_arch_init(void)
|
---|
753 | {
|
---|
754 | }
|
---|
755 |
|
---|
756 | void tlb_print(void)
|
---|
757 | {
|
---|
758 | }
|
---|
759 |
|
---|
760 | /** @}
|
---|
761 | */
|
---|