| 1 | #
|
|---|
| 2 | # Copyright (c) 2005 Jakub Vana
|
|---|
| 3 | # Copyright (c) 2005 Jakub Jermar
|
|---|
| 4 | # All rights reserved.
|
|---|
| 5 | #
|
|---|
| 6 | # Redistribution and use in source and binary forms, with or without
|
|---|
| 7 | # modification, are permitted provided that the following conditions
|
|---|
| 8 | # are met:
|
|---|
| 9 | #
|
|---|
| 10 | # - Redistributions of source code must retain the above copyright
|
|---|
| 11 | # notice, this list of conditions and the following disclaimer.
|
|---|
| 12 | # - Redistributions in binary form must reproduce the above copyright
|
|---|
| 13 | # notice, this list of conditions and the following disclaimer in the
|
|---|
| 14 | # documentation and/or other materials provided with the distribution.
|
|---|
| 15 | # - The name of the author may not be used to endorse or promote products
|
|---|
| 16 | # derived from this software without specific prior written permission.
|
|---|
| 17 | #
|
|---|
| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|---|
| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|---|
| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|---|
| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|---|
| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|---|
| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|---|
| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|---|
| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|---|
| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|---|
| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|---|
| 28 | #
|
|---|
| 29 |
|
|---|
| 30 | #include <arch/stack.h>
|
|---|
| 31 | #include <arch/register.h>
|
|---|
| 32 | #include <arch/mm/page.h>
|
|---|
| 33 | #include <align.h>
|
|---|
| 34 |
|
|---|
| 35 | #define FRS_TO_SAVE 30
|
|---|
| 36 | #define STACK_ITEMS (21 + FRS_TO_SAVE * 2)
|
|---|
| 37 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
|
|---|
| 38 |
|
|---|
| 39 | #if (STACK_ITEMS % 2 == 0)
|
|---|
| 40 | # define STACK_FRAME_BIAS 8
|
|---|
| 41 | #else
|
|---|
| 42 | # define STACK_FRAME_BIAS 16
|
|---|
| 43 | #endif
|
|---|
| 44 |
|
|---|
| 45 | /** Partitioning of bank 0 registers. */
|
|---|
| 46 | #define R_OFFS r16
|
|---|
| 47 | #define R_HANDLER r17
|
|---|
| 48 | #define R_RET r18
|
|---|
| 49 | #define R_TMP r19
|
|---|
| 50 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
|
|---|
| 51 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
|
|---|
| 52 |
|
|---|
| 53 | /* Speculation vector handler */
|
|---|
| 54 | .macro SPECULATION_VECTOR_HANDLER offs
|
|---|
| 55 | .org ivt + \offs
|
|---|
| 56 |
|
|---|
| 57 | /* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
|
|---|
| 58 | mov r16 = pr
|
|---|
| 59 | mov r17 = cr.iim
|
|---|
| 60 | mov r18 = cr.iip
|
|---|
| 61 | mov r19 = cr.ipsr
|
|---|
| 62 | mov r20 = cr.isr ;;
|
|---|
| 63 |
|
|---|
| 64 | /* 2. Move IIP to IIPA. */
|
|---|
| 65 | mov cr.iipa = r18
|
|---|
| 66 |
|
|---|
| 67 | /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
|
|---|
| 68 | shl r17 = r17, 43 ;; /* shift bit 20 to bit 63 */
|
|---|
| 69 | shr r17 = r17, 39 ;; /* signed shift right to bit 24 */
|
|---|
| 70 | add r18 = r18, r17 ;;
|
|---|
| 71 | mov cr.iip = r18
|
|---|
| 72 |
|
|---|
| 73 | /* 4. Set IPSR.ri to 0. */
|
|---|
| 74 | dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
|
|---|
| 75 | mov cr.ipsr = r19
|
|---|
| 76 |
|
|---|
| 77 | /* 5. Check whether IPSR.tb or IPSR.ss is set. */
|
|---|
| 78 |
|
|---|
| 79 | /* TODO:
|
|---|
| 80 | * Implement this when Taken Branch and Single Step traps can occur.
|
|---|
| 81 | */
|
|---|
| 82 |
|
|---|
| 83 | /* 6. Restore predicates and return from interruption. */
|
|---|
| 84 | mov pr = r16 ;;
|
|---|
| 85 | rfi
|
|---|
| 86 | .endm
|
|---|
| 87 |
|
|---|
| 88 | /** Heavyweight interrupt handler
|
|---|
| 89 | *
|
|---|
| 90 | * This macro roughly follows steps from 1 to 19 described in
|
|---|
| 91 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
|
|---|
| 92 | *
|
|---|
| 93 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
|
|---|
| 94 | * This goal is achieved by using procedure calls after RSE becomes operational.
|
|---|
| 95 | *
|
|---|
| 96 | * Some steps are skipped (enabling and disabling interrupts).
|
|---|
| 97 | *
|
|---|
| 98 | * @param offs Offset from the beginning of IVT.
|
|---|
| 99 | * @param handler Interrupt handler address.
|
|---|
| 100 | */
|
|---|
| 101 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
|
|---|
| 102 | .org ivt + \offs
|
|---|
| 103 | mov R_OFFS = \offs
|
|---|
| 104 | movl R_HANDLER = \handler ;;
|
|---|
| 105 | br heavyweight_handler
|
|---|
| 106 | .endm
|
|---|
| 107 |
|
|---|
| 108 | .global heavyweight_handler
|
|---|
| 109 | heavyweight_handler:
|
|---|
| 110 | /* 1. copy interrupt registers into bank 0 */
|
|---|
| 111 |
|
|---|
| 112 | /*
|
|---|
| 113 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
|
|---|
| 114 | */
|
|---|
| 115 |
|
|---|
| 116 | /* Set up FPU as in interrupted context. */
|
|---|
| 117 | mov r24 = psr
|
|---|
| 118 | mov r25 = cr.ipsr
|
|---|
| 119 | mov r26 = PSR_DFH_MASK
|
|---|
| 120 | mov r27 = ~PSR_DFH_MASK ;;
|
|---|
| 121 | and r26 = r25, r26
|
|---|
| 122 | and r24 = r24, r27;;
|
|---|
| 123 | or r24 = r24, r26;;
|
|---|
| 124 | mov psr.l = r24;;
|
|---|
| 125 | srlz.i
|
|---|
| 126 | srlz.d;;
|
|---|
| 127 |
|
|---|
| 128 | mov r24 = cr.iip
|
|---|
| 129 | mov r25 = cr.ipsr
|
|---|
| 130 | mov r26 = cr.iipa
|
|---|
| 131 | mov r27 = cr.isr
|
|---|
| 132 | mov r28 = cr.ifa
|
|---|
| 133 |
|
|---|
| 134 | /* 2. preserve predicate register into bank 0 */
|
|---|
| 135 | mov r29 = pr ;;
|
|---|
| 136 |
|
|---|
| 137 | /* 3. switch to kernel memory stack */
|
|---|
| 138 | mov r30 = cr.ipsr
|
|---|
| 139 | shr.u r31 = r12, VRN_SHIFT ;;
|
|---|
| 140 |
|
|---|
| 141 | shr.u r30 = r30, PSR_CPL_SHIFT ;;
|
|---|
| 142 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
|
|---|
| 143 |
|
|---|
| 144 | /*
|
|---|
| 145 | * Set p3 to true if the interrupted context executed in kernel mode.
|
|---|
| 146 | * Set p4 to false if the interrupted context didn't execute in kernel mode.
|
|---|
| 147 | */
|
|---|
| 148 | cmp.eq p3, p4 = r30, r0 ;;
|
|---|
| 149 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
|
|---|
| 150 |
|
|---|
| 151 | /*
|
|---|
| 152 | * Set p3 to true if the stack register references kernel address space.
|
|---|
| 153 | * Set p4 to false if the stack register doesn't reference kernel address space.
|
|---|
| 154 | */
|
|---|
| 155 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
|
|---|
| 156 |
|
|---|
| 157 | /*
|
|---|
| 158 | * Now, p4 is true iff the stack needs to be switched to kernel stack.
|
|---|
| 159 | */
|
|---|
| 160 | mov r30 = r12
|
|---|
| 161 | (p4) mov r12 = R_KSTACK ;;
|
|---|
| 162 |
|
|---|
| 163 | add r31 = -STACK_FRAME_BIAS, r12 ;;
|
|---|
| 164 | add r12 = -STACK_FRAME_SIZE, r12
|
|---|
| 165 |
|
|---|
| 166 | /* 4. save registers in bank 0 into memory stack */
|
|---|
| 167 |
|
|---|
| 168 | /*
|
|---|
| 169 | * If this is break_instruction handler,
|
|---|
| 170 | * copy input parameters to stack.
|
|---|
| 171 | */
|
|---|
| 172 | mov R_TMP = 0x2c00 ;;
|
|---|
| 173 | cmp.eq p6, p5 = R_OFFS, R_TMP ;;
|
|---|
| 174 |
|
|---|
| 175 | /*
|
|---|
| 176 | * From now on, if this is break_instruction handler, p6 is true and p5
|
|---|
| 177 | * is false. Otherwise p6 is false and p5 is true.
|
|---|
| 178 | * Note that p5 is a preserved predicate register and we make use of it.
|
|---|
| 179 | */
|
|---|
| 180 |
|
|---|
| 181 | (p6) st8 [r31] = r38, -8 ;; /* save in6 */
|
|---|
| 182 | (p6) st8 [r31] = r37, -8 ;; /* save in5 */
|
|---|
| 183 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */
|
|---|
| 184 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */
|
|---|
| 185 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */
|
|---|
| 186 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */
|
|---|
| 187 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */
|
|---|
| 188 | (p5) add r31 = -56, r31 ;;
|
|---|
| 189 |
|
|---|
| 190 | st8 [r31] = r30, -8 ;; /* save old stack pointer */
|
|---|
| 191 |
|
|---|
| 192 | st8 [r31] = r29, -8 ;; /* save predicate registers */
|
|---|
| 193 |
|
|---|
| 194 | st8 [r31] = r24, -8 ;; /* save cr.iip */
|
|---|
| 195 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */
|
|---|
| 196 | st8 [r31] = r26, -8 ;; /* save cr.iipa */
|
|---|
| 197 | st8 [r31] = r27, -8 ;; /* save cr.isr */
|
|---|
| 198 | st8 [r31] = r28, -8 ;; /* save cr.ifa */
|
|---|
| 199 |
|
|---|
| 200 | /* 5. RSE switch from interrupted context */
|
|---|
| 201 | mov r24 = ar.rsc
|
|---|
| 202 | mov r25 = ar.pfs
|
|---|
| 203 | cover
|
|---|
| 204 | mov r26 = cr.ifs
|
|---|
| 205 |
|
|---|
| 206 | st8 [r31] = r24, -8 ;; /* save ar.rsc */
|
|---|
| 207 | st8 [r31] = r25, -8 ;; /* save ar.pfs */
|
|---|
| 208 | st8 [r31] = r26, -8 /* save ar.ifs */
|
|---|
| 209 |
|
|---|
| 210 | and r24 = ~(RSC_PL_MASK), r24 ;;
|
|---|
| 211 | and r30 = ~(RSC_MODE_MASK), r24 ;;
|
|---|
| 212 | mov ar.rsc = r30 ;; /* update RSE state */
|
|---|
| 213 |
|
|---|
| 214 | mov r27 = ar.rnat
|
|---|
| 215 | mov r28 = ar.bspstore ;;
|
|---|
| 216 |
|
|---|
| 217 | /*
|
|---|
| 218 | * Inspect BSPSTORE to figure out whether it is necessary to switch to
|
|---|
| 219 | * kernel BSPSTORE.
|
|---|
| 220 | */
|
|---|
| 221 | (p1) shr.u r30 = r28, VRN_SHIFT ;;
|
|---|
| 222 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
|
|---|
| 223 |
|
|---|
| 224 | /*
|
|---|
| 225 | * If BSPSTORE needs to be switched, p1 is false and p2 is true.
|
|---|
| 226 | */
|
|---|
| 227 | (p1) mov r30 = r28
|
|---|
| 228 | (p2) mov r30 = R_KSTACK_BSP ;;
|
|---|
| 229 | (p2) mov ar.bspstore = r30 ;;
|
|---|
| 230 |
|
|---|
| 231 | mov r29 = ar.bsp
|
|---|
| 232 |
|
|---|
| 233 | st8 [r31] = r27, -8 ;; /* save ar.rnat */
|
|---|
| 234 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */
|
|---|
| 235 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */
|
|---|
| 236 | st8 [r31] = r29, -8 /* save ar.bsp */
|
|---|
| 237 |
|
|---|
| 238 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
|
|---|
| 239 |
|
|---|
| 240 | /* steps 6 - 15 are done by heavyweight_handler_inner() */
|
|---|
| 241 | mov R_RET = b0 /* save b0 belonging to interrupted context */
|
|---|
| 242 | br.call.sptk.many b0 = heavyweight_handler_inner
|
|---|
| 243 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
|
|---|
| 244 |
|
|---|
| 245 | /* 16. RSE switch to interrupted context */
|
|---|
| 246 | cover /* allocate zero size frame (step 1 (from Intel Docs)) */
|
|---|
| 247 |
|
|---|
| 248 | add r31 = (STACK_SCRATCH_AREA_SIZE + (FRS_TO_SAVE * 2 * 8)), r12 ;;
|
|---|
| 249 |
|
|---|
| 250 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */
|
|---|
| 251 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
|
|---|
| 252 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
|
|---|
| 253 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
|
|---|
| 254 | shl r27 = r27, 16
|
|---|
| 255 |
|
|---|
| 256 | mov r24 = ar.rsc ;;
|
|---|
| 257 | and r30 = ~3, r24 ;;
|
|---|
| 258 | or r24 = r30 , r27 ;;
|
|---|
| 259 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
|
|---|
| 260 |
|
|---|
| 261 | loadrs /* (step 3) */
|
|---|
| 262 |
|
|---|
| 263 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */
|
|---|
| 264 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */
|
|---|
| 265 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */
|
|---|
| 266 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */
|
|---|
| 267 |
|
|---|
| 268 | mov ar.bspstore = r29 ;; /* (step 4) */
|
|---|
| 269 | mov ar.rnat = r27 /* (step 5) */
|
|---|
| 270 |
|
|---|
| 271 | mov ar.pfs = r25 /* (step 6) */
|
|---|
| 272 | mov cr.ifs = r26
|
|---|
| 273 |
|
|---|
| 274 | mov ar.rsc = r24 /* (step 7) */
|
|---|
| 275 |
|
|---|
| 276 | /* 17. restore interruption state from memory stack */
|
|---|
| 277 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */
|
|---|
| 278 | ld8 r27 = [r31], +8 ;; /* load cr.isr */
|
|---|
| 279 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */
|
|---|
| 280 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
|
|---|
| 281 | ld8 r24 = [r31], +8 ;; /* load cr.iip */
|
|---|
| 282 |
|
|---|
| 283 | mov cr.iip = r24;;
|
|---|
| 284 | mov cr.iipa = r26
|
|---|
| 285 | mov cr.isr = r27
|
|---|
| 286 | mov cr.ifa = r28
|
|---|
| 287 |
|
|---|
| 288 | /* Set up FPU as in exception. */
|
|---|
| 289 | mov r24 = psr
|
|---|
| 290 | mov r26 = PSR_DFH_MASK
|
|---|
| 291 | mov r27 = ~PSR_DFH_MASK ;;
|
|---|
| 292 | and r25 = r25, r27
|
|---|
| 293 | and r24 = r24, r26 ;;
|
|---|
| 294 | or r25 = r25, r24;;
|
|---|
| 295 | mov cr.ipsr = r25
|
|---|
| 296 |
|
|---|
| 297 | /* 18. restore predicate registers from memory stack */
|
|---|
| 298 | ld8 r29 = [r31], +8 ;; /* load predicate registers */
|
|---|
| 299 | mov pr = r29
|
|---|
| 300 |
|
|---|
| 301 | /* 19. return from interruption */
|
|---|
| 302 | ld8 r12 = [r31] /* load stack pointer */
|
|---|
| 303 | rfi ;;
|
|---|
| 304 |
|
|---|
| 305 | .global heavyweight_handler_inner
|
|---|
| 306 | heavyweight_handler_inner:
|
|---|
| 307 | /*
|
|---|
| 308 | * From this point, the rest of the interrupted context
|
|---|
| 309 | * will be preserved in stacked registers and backing store.
|
|---|
| 310 | */
|
|---|
| 311 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
|
|---|
| 312 |
|
|---|
| 313 | /* bank 0 is going to be shadowed, copy essential data from there */
|
|---|
| 314 | mov loc1 = R_RET /* b0 belonging to interrupted context */
|
|---|
| 315 | mov loc2 = R_HANDLER
|
|---|
| 316 | mov out0 = R_OFFS
|
|---|
| 317 |
|
|---|
| 318 | add out1 = STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 319 |
|
|---|
| 320 | /* 6. switch to bank 1 and reenable PSR.ic */
|
|---|
| 321 | ssm PSR_IC_MASK
|
|---|
| 322 | bsw.1 ;;
|
|---|
| 323 | srlz.d
|
|---|
| 324 |
|
|---|
| 325 | /* 7. preserve branch and application registers */
|
|---|
| 326 | mov loc3 = ar.unat
|
|---|
| 327 | mov loc4 = ar.lc
|
|---|
| 328 | mov loc5 = ar.ec
|
|---|
| 329 | mov loc6 = ar.ccv
|
|---|
| 330 | mov loc7 = ar.csd
|
|---|
| 331 | mov loc8 = ar.ssd
|
|---|
| 332 |
|
|---|
| 333 | mov loc9 = b0
|
|---|
| 334 | mov loc10 = b1
|
|---|
| 335 | mov loc11 = b2
|
|---|
| 336 | mov loc12 = b3
|
|---|
| 337 | mov loc13 = b4
|
|---|
| 338 | mov loc14 = b5
|
|---|
| 339 | mov loc15 = b6
|
|---|
| 340 | mov loc16 = b7
|
|---|
| 341 |
|
|---|
| 342 | /* 8. preserve general and floating-point registers */
|
|---|
| 343 | mov loc17 = r1
|
|---|
| 344 | mov loc18 = r2
|
|---|
| 345 | mov loc19 = r3
|
|---|
| 346 | mov loc20 = r4
|
|---|
| 347 | mov loc21 = r5
|
|---|
| 348 | mov loc22 = r6
|
|---|
| 349 | mov loc23 = r7
|
|---|
| 350 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */
|
|---|
| 351 | mov loc25 = r9
|
|---|
| 352 | mov loc26 = r10
|
|---|
| 353 | mov loc27 = r11
|
|---|
| 354 | /* skip r12 (stack pointer) */
|
|---|
| 355 | mov loc28 = r13
|
|---|
| 356 | mov loc29 = r14
|
|---|
| 357 | mov loc30 = r15
|
|---|
| 358 | mov loc31 = r16
|
|---|
| 359 | mov loc32 = r17
|
|---|
| 360 | mov loc33 = r18
|
|---|
| 361 | mov loc34 = r19
|
|---|
| 362 | mov loc35 = r20
|
|---|
| 363 | mov loc36 = r21
|
|---|
| 364 | mov loc37 = r22
|
|---|
| 365 | mov loc38 = r23
|
|---|
| 366 | mov loc39 = r24
|
|---|
| 367 | mov loc40 = r25
|
|---|
| 368 | mov loc41 = r26
|
|---|
| 369 | mov loc42 = r27
|
|---|
| 370 | mov loc43 = r28
|
|---|
| 371 | mov loc44 = r29
|
|---|
| 372 | mov loc45 = r30
|
|---|
| 373 | mov loc46 = r31
|
|---|
| 374 |
|
|---|
| 375 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 376 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 377 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 378 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 379 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 380 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 381 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 382 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
|
|---|
| 383 |
|
|---|
| 384 | stf.spill [r26] = f2, 0x80
|
|---|
| 385 | stf.spill [r27] = f3, 0x80
|
|---|
| 386 | stf.spill [r28] = f4, 0x80
|
|---|
| 387 | stf.spill [r29] = f5, 0x80
|
|---|
| 388 | stf.spill [r30] = f6, 0x80
|
|---|
| 389 | stf.spill [r31] = f7, 0x80 ;;
|
|---|
| 390 |
|
|---|
| 391 | stf.spill [r24] = f8, 0x80
|
|---|
| 392 | stf.spill [r25] = f9, 0x80
|
|---|
| 393 | stf.spill [r26] = f10, 0x80
|
|---|
| 394 | stf.spill [r27] = f11, 0x80
|
|---|
| 395 | stf.spill [r28] = f12, 0x80
|
|---|
| 396 | stf.spill [r29] = f13, 0x80
|
|---|
| 397 | stf.spill [r30] = f14, 0x80
|
|---|
| 398 | stf.spill [r31] = f15, 0x80 ;;
|
|---|
| 399 |
|
|---|
| 400 | stf.spill [r24] = f16, 0x80
|
|---|
| 401 | stf.spill [r25] = f17, 0x80
|
|---|
| 402 | stf.spill [r26] = f18, 0x80
|
|---|
| 403 | stf.spill [r27] = f19, 0x80
|
|---|
| 404 | stf.spill [r28] = f20, 0x80
|
|---|
| 405 | stf.spill [r29] = f21, 0x80
|
|---|
| 406 | stf.spill [r30] = f22, 0x80
|
|---|
| 407 | stf.spill [r31] = f23, 0x80 ;;
|
|---|
| 408 |
|
|---|
| 409 | stf.spill [r24] = f24, 0x80
|
|---|
| 410 | stf.spill [r25] = f25, 0x80
|
|---|
| 411 | stf.spill [r26] = f26, 0x80
|
|---|
| 412 | stf.spill [r27] = f27, 0x80
|
|---|
| 413 | stf.spill [r28] = f28, 0x80
|
|---|
| 414 | stf.spill [r29] = f29, 0x80
|
|---|
| 415 | stf.spill [r30] = f30, 0x80
|
|---|
| 416 | stf.spill [r31] = f31, 0x80 ;;
|
|---|
| 417 |
|
|---|
| 418 | mov loc47 = ar.fpsr /* preserve floating point status register */
|
|---|
| 419 |
|
|---|
| 420 | /* 9. skipped (will not enable interrupts) */
|
|---|
| 421 | /*
|
|---|
| 422 | * ssm PSR_I_MASK
|
|---|
| 423 | * ;;
|
|---|
| 424 | * srlz.d
|
|---|
| 425 | */
|
|---|
| 426 |
|
|---|
| 427 | /* 10. call handler */
|
|---|
| 428 | movl r1 = __gp
|
|---|
| 429 |
|
|---|
| 430 | mov b1 = loc2
|
|---|
| 431 | br.call.sptk.many b0 = b1
|
|---|
| 432 |
|
|---|
| 433 | /* 11. return from handler */
|
|---|
| 434 | 0:
|
|---|
| 435 |
|
|---|
| 436 | /* 12. skipped (will not disable interrupts) */
|
|---|
| 437 | /*
|
|---|
| 438 | * rsm PSR_I_MASK
|
|---|
| 439 | * ;;
|
|---|
| 440 | * srlz.d
|
|---|
| 441 | */
|
|---|
| 442 |
|
|---|
| 443 | /* 13. restore general and floating-point registers */
|
|---|
| 444 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 445 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 446 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 447 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 448 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 449 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 450 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 451 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
|
|---|
| 452 |
|
|---|
| 453 | ldf.fill f2 = [r26], 0x80
|
|---|
| 454 | ldf.fill f3 = [r27], 0x80
|
|---|
| 455 | ldf.fill f4 = [r28], 0x80
|
|---|
| 456 | ldf.fill f5 = [r29], 0x80
|
|---|
| 457 | ldf.fill f6 = [r30], 0x80
|
|---|
| 458 | ldf.fill f7 = [r31], 0x80 ;;
|
|---|
| 459 |
|
|---|
| 460 | ldf.fill f8 = [r24], 0x80
|
|---|
| 461 | ldf.fill f9 = [r25], 0x80
|
|---|
| 462 | ldf.fill f10 = [r26], 0x80
|
|---|
| 463 | ldf.fill f11 = [r27], 0x80
|
|---|
| 464 | ldf.fill f12 = [r28], 0x80
|
|---|
| 465 | ldf.fill f13 = [r29], 0x80
|
|---|
| 466 | ldf.fill f14 = [r30], 0x80
|
|---|
| 467 | ldf.fill f15 = [r31], 0x80 ;;
|
|---|
| 468 |
|
|---|
| 469 | ldf.fill f16 = [r24], 0x80
|
|---|
| 470 | ldf.fill f17 = [r25], 0x80
|
|---|
| 471 | ldf.fill f18 = [r26], 0x80
|
|---|
| 472 | ldf.fill f19 = [r27], 0x80
|
|---|
| 473 | ldf.fill f20 = [r28], 0x80
|
|---|
| 474 | ldf.fill f21 = [r29], 0x80
|
|---|
| 475 | ldf.fill f22 = [r30], 0x80
|
|---|
| 476 | ldf.fill f23 = [r31], 0x80 ;;
|
|---|
| 477 |
|
|---|
| 478 | ldf.fill f24 = [r24], 0x80
|
|---|
| 479 | ldf.fill f25 = [r25], 0x80
|
|---|
| 480 | ldf.fill f26 = [r26], 0x80
|
|---|
| 481 | ldf.fill f27 = [r27], 0x80
|
|---|
| 482 | ldf.fill f28 = [r28], 0x80
|
|---|
| 483 | ldf.fill f29 = [r29], 0x80
|
|---|
| 484 | ldf.fill f30 = [r30], 0x80
|
|---|
| 485 | ldf.fill f31 = [r31], 0x80 ;;
|
|---|
| 486 |
|
|---|
| 487 | mov r1 = loc17
|
|---|
| 488 | mov r2 = loc18
|
|---|
| 489 | mov r3 = loc19
|
|---|
| 490 | mov r4 = loc20
|
|---|
| 491 | mov r5 = loc21
|
|---|
| 492 | mov r6 = loc22
|
|---|
| 493 | mov r7 = loc23
|
|---|
| 494 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */
|
|---|
| 495 | mov r9 = loc25
|
|---|
| 496 | mov r10 = loc26
|
|---|
| 497 | mov r11 = loc27
|
|---|
| 498 | /* skip r12 (stack pointer) */
|
|---|
| 499 | mov r13 = loc28
|
|---|
| 500 | mov r14 = loc29
|
|---|
| 501 | mov r15 = loc30
|
|---|
| 502 | mov r16 = loc31
|
|---|
| 503 | mov r17 = loc32
|
|---|
| 504 | mov r18 = loc33
|
|---|
| 505 | mov r19 = loc34
|
|---|
| 506 | mov r20 = loc35
|
|---|
| 507 | mov r21 = loc36
|
|---|
| 508 | mov r22 = loc37
|
|---|
| 509 | mov r23 = loc38
|
|---|
| 510 | mov r24 = loc39
|
|---|
| 511 | mov r25 = loc40
|
|---|
| 512 | mov r26 = loc41
|
|---|
| 513 | mov r27 = loc42
|
|---|
| 514 | mov r28 = loc43
|
|---|
| 515 | mov r29 = loc44
|
|---|
| 516 | mov r30 = loc45
|
|---|
| 517 | mov r31 = loc46
|
|---|
| 518 |
|
|---|
| 519 | mov ar.fpsr = loc47 /* restore floating point status register */
|
|---|
| 520 |
|
|---|
| 521 | /* 14. restore branch and application registers */
|
|---|
| 522 | mov ar.unat = loc3
|
|---|
| 523 | mov ar.lc = loc4
|
|---|
| 524 | mov ar.ec = loc5
|
|---|
| 525 | mov ar.ccv = loc6
|
|---|
| 526 | mov ar.csd = loc7
|
|---|
| 527 | mov ar.ssd = loc8
|
|---|
| 528 |
|
|---|
| 529 | mov b0 = loc9
|
|---|
| 530 | mov b1 = loc10
|
|---|
| 531 | mov b2 = loc11
|
|---|
| 532 | mov b3 = loc12
|
|---|
| 533 | mov b4 = loc13
|
|---|
| 534 | mov b5 = loc14
|
|---|
| 535 | mov b6 = loc15
|
|---|
| 536 | mov b7 = loc16
|
|---|
| 537 |
|
|---|
| 538 | /* 15. disable PSR.ic and switch to bank 0 */
|
|---|
| 539 | rsm PSR_IC_MASK
|
|---|
| 540 | bsw.0 ;;
|
|---|
| 541 | srlz.d
|
|---|
| 542 |
|
|---|
| 543 | mov R_RET = loc1
|
|---|
| 544 | mov ar.pfs = loc0
|
|---|
| 545 | br.ret.sptk.many b0
|
|---|
| 546 |
|
|---|
| 547 | .global ivt
|
|---|
| 548 | .align 32768
|
|---|
| 549 | ivt:
|
|---|
| 550 | HEAVYWEIGHT_HANDLER 0x0000
|
|---|
| 551 | HEAVYWEIGHT_HANDLER 0x0400
|
|---|
| 552 | HEAVYWEIGHT_HANDLER 0x0800
|
|---|
| 553 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
|
|---|
| 554 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
|
|---|
| 555 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
|
|---|
| 556 | HEAVYWEIGHT_HANDLER 0x1800
|
|---|
| 557 | HEAVYWEIGHT_HANDLER 0x1c00
|
|---|
| 558 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
|
|---|
| 559 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
|
|---|
| 560 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
|
|---|
| 561 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
|
|---|
| 562 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
|
|---|
| 563 | HEAVYWEIGHT_HANDLER 0x3400
|
|---|
| 564 | HEAVYWEIGHT_HANDLER 0x3800
|
|---|
| 565 | HEAVYWEIGHT_HANDLER 0x3c00
|
|---|
| 566 | HEAVYWEIGHT_HANDLER 0x4000
|
|---|
| 567 | HEAVYWEIGHT_HANDLER 0x4400
|
|---|
| 568 | HEAVYWEIGHT_HANDLER 0x4800
|
|---|
| 569 | HEAVYWEIGHT_HANDLER 0x4c00
|
|---|
| 570 |
|
|---|
| 571 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present
|
|---|
| 572 | HEAVYWEIGHT_HANDLER 0x5100
|
|---|
| 573 | HEAVYWEIGHT_HANDLER 0x5200
|
|---|
| 574 | HEAVYWEIGHT_HANDLER 0x5300 data_access_rights_fault
|
|---|
| 575 | HEAVYWEIGHT_HANDLER 0x5400 general_exception
|
|---|
| 576 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
|
|---|
| 577 | HEAVYWEIGHT_HANDLER 0x5600
|
|---|
| 578 | SPECULATION_VECTOR_HANDLER 0x5700
|
|---|
| 579 | HEAVYWEIGHT_HANDLER 0x5800
|
|---|
| 580 | HEAVYWEIGHT_HANDLER 0x5900
|
|---|
| 581 | HEAVYWEIGHT_HANDLER 0x5a00
|
|---|
| 582 | HEAVYWEIGHT_HANDLER 0x5b00
|
|---|
| 583 | HEAVYWEIGHT_HANDLER 0x5c00
|
|---|
| 584 | HEAVYWEIGHT_HANDLER 0x5d00
|
|---|
| 585 | HEAVYWEIGHT_HANDLER 0x5e00
|
|---|
| 586 | HEAVYWEIGHT_HANDLER 0x5f00
|
|---|
| 587 |
|
|---|
| 588 | HEAVYWEIGHT_HANDLER 0x6000
|
|---|
| 589 | HEAVYWEIGHT_HANDLER 0x6100
|
|---|
| 590 | HEAVYWEIGHT_HANDLER 0x6200
|
|---|
| 591 | HEAVYWEIGHT_HANDLER 0x6300
|
|---|
| 592 | HEAVYWEIGHT_HANDLER 0x6400
|
|---|
| 593 | HEAVYWEIGHT_HANDLER 0x6500
|
|---|
| 594 | HEAVYWEIGHT_HANDLER 0x6600
|
|---|
| 595 | HEAVYWEIGHT_HANDLER 0x6700
|
|---|
| 596 | HEAVYWEIGHT_HANDLER 0x6800
|
|---|
| 597 | HEAVYWEIGHT_HANDLER 0x6900
|
|---|
| 598 | HEAVYWEIGHT_HANDLER 0x6a00
|
|---|
| 599 | HEAVYWEIGHT_HANDLER 0x6b00
|
|---|
| 600 | HEAVYWEIGHT_HANDLER 0x6c00
|
|---|
| 601 | HEAVYWEIGHT_HANDLER 0x6d00
|
|---|
| 602 | HEAVYWEIGHT_HANDLER 0x6e00
|
|---|
| 603 | HEAVYWEIGHT_HANDLER 0x6f00
|
|---|
| 604 |
|
|---|
| 605 | HEAVYWEIGHT_HANDLER 0x7000
|
|---|
| 606 | HEAVYWEIGHT_HANDLER 0x7100
|
|---|
| 607 | HEAVYWEIGHT_HANDLER 0x7200
|
|---|
| 608 | HEAVYWEIGHT_HANDLER 0x7300
|
|---|
| 609 | HEAVYWEIGHT_HANDLER 0x7400
|
|---|
| 610 | HEAVYWEIGHT_HANDLER 0x7500
|
|---|
| 611 | HEAVYWEIGHT_HANDLER 0x7600
|
|---|
| 612 | HEAVYWEIGHT_HANDLER 0x7700
|
|---|
| 613 | HEAVYWEIGHT_HANDLER 0x7800
|
|---|
| 614 | HEAVYWEIGHT_HANDLER 0x7900
|
|---|
| 615 | HEAVYWEIGHT_HANDLER 0x7a00
|
|---|
| 616 | HEAVYWEIGHT_HANDLER 0x7b00
|
|---|
| 617 | HEAVYWEIGHT_HANDLER 0x7c00
|
|---|
| 618 | HEAVYWEIGHT_HANDLER 0x7d00
|
|---|
| 619 | HEAVYWEIGHT_HANDLER 0x7e00
|
|---|
| 620 | HEAVYWEIGHT_HANDLER 0x7f00
|
|---|
