| 1 | #
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| 2 | # Copyright (c) 2005 Jakub Vana
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| 3 | # Copyright (c) 2005 Jakub Jermar
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| 4 | # All rights reserved.
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| 5 | #
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| 6 | # Redistribution and use in source and binary forms, with or without
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| 7 | # modification, are permitted provided that the following conditions
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| 8 | # are met:
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| 9 | #
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| 10 | # - Redistributions of source code must retain the above copyright
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| 11 | # notice, this list of conditions and the following disclaimer.
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| 12 | # - Redistributions in binary form must reproduce the above copyright
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| 13 | # notice, this list of conditions and the following disclaimer in the
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| 14 | # documentation and/or other materials provided with the distribution.
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| 15 | # - The name of the author may not be used to endorse or promote products
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| 16 | # derived from this software without specific prior written permission.
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| 17 | #
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| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | #
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| 29 |
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| 30 | #include <arch/stack.h>
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| 31 | #include <arch/register.h>
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| 32 | #include <arch/mm/page.h>
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| 33 | #include <align.h>
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| 34 |
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| 35 | #define FRS_TO_SAVE 30
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| 36 | #define STACK_ITEMS (21 + FRS_TO_SAVE * 2)
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| 37 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
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| 38 |
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| 39 | #if (STACK_ITEMS % 2 == 0)
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| 40 | # define STACK_FRAME_BIAS 8
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| 41 | #else
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| 42 | # define STACK_FRAME_BIAS 16
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| 43 | #endif
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| 44 |
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| 45 | /** Partitioning of bank 0 registers. */
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| 46 | #define R_OFFS r16
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| 47 | #define R_HANDLER r17
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| 48 | #define R_RET r18
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| 49 | #define R_TMP r19
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| 50 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
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| 51 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
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| 52 |
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| 53 | /** Heavyweight interrupt handler
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| 54 | *
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| 55 | * This macro roughly follows steps from 1 to 19 described in
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| 56 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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| 57 | *
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| 58 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
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| 59 | * This goal is achieved by using procedure calls after RSE becomes operational.
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| 60 | *
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| 61 | * Some steps are skipped (enabling and disabling interrupts).
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| 62 | *
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| 63 | * @param offs Offset from the beginning of IVT.
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| 64 | * @param handler Interrupt handler address.
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| 65 | */
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| 66 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
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| 67 | .org ivt + \offs
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| 68 | mov R_OFFS = \offs
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| 69 | movl R_HANDLER = \handler ;;
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| 70 | br heavyweight_handler
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| 71 | .endm
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| 72 |
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| 73 | .global heavyweight_handler
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| 74 | heavyweight_handler:
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| 75 | /* 1. copy interrupt registers into bank 0 */
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| 76 |
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| 77 | /*
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| 78 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
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| 79 | */
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| 80 |
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| 81 | /* Set up FPU as in interrupted context. */
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| 82 | mov r24 = psr
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| 83 | mov r25 = cr.ipsr
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| 84 | mov r26 = PSR_DFH_MASK
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| 85 | mov r27 = ~PSR_DFH_MASK ;;
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| 86 | and r26 = r25, r26
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| 87 | and r24 = r24, r27;;
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| 88 | or r24 = r24, r26;;
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| 89 | mov psr.l = r24;;
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| 90 | srlz.i
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| 91 | srlz.d;;
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| 92 |
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| 93 | mov r24 = cr.iip
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| 94 | mov r25 = cr.ipsr
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| 95 | mov r26 = cr.iipa
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| 96 | mov r27 = cr.isr
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| 97 | mov r28 = cr.ifa
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| 98 |
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| 99 | /* 2. preserve predicate register into bank 0 */
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| 100 | mov r29 = pr ;;
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| 101 |
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| 102 | /* 3. switch to kernel memory stack */
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| 103 | mov r30 = cr.ipsr
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| 104 | shr.u r31 = r12, VRN_SHIFT ;;
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| 105 |
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| 106 | shr.u r30 = r30, PSR_CPL_SHIFT ;;
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| 107 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
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| 108 |
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| 109 | /*
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| 110 | * Set p3 to true if the interrupted context executed in kernel mode.
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| 111 | * Set p4 to false if the interrupted context didn't execute in kernel mode.
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| 112 | */
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| 113 | cmp.eq p3, p4 = r30, r0 ;;
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| 114 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
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| 115 |
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| 116 | /*
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| 117 | * Set p3 to true if the stack register references kernel address space.
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| 118 | * Set p4 to false if the stack register doesn't reference kernel address space.
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| 119 | */
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| 120 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
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| 121 |
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| 122 | /*
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| 123 | * Now, p4 is true iff the stack needs to be switched to kernel stack.
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| 124 | */
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| 125 | mov r30 = r12
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| 126 | (p4) mov r12 = R_KSTACK ;;
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| 127 |
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| 128 | add r31 = -STACK_FRAME_BIAS, r12 ;;
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| 129 | add r12 = -STACK_FRAME_SIZE, r12
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| 130 |
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| 131 | /* 4. save registers in bank 0 into memory stack */
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| 132 |
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| 133 | /*
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| 134 | * If this is break_instruction handler,
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| 135 | * copy input parameters to stack.
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| 136 | */
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| 137 | mov R_TMP = 0x2c00 ;;
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| 138 | cmp.eq p6, p5 = R_OFFS, R_TMP ;;
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| 139 |
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| 140 | /*
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| 141 | * From now on, if this is break_instruction handler, p6 is true and p5
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| 142 | * is false. Otherwise p6 is false and p5 is true.
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| 143 | * Note that p5 is a preserved predicate register and we make use of it.
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| 144 | */
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| 145 |
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| 146 | (p6) st8 [r31] = r38, -8 ;; /* save in6 */
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| 147 | (p6) st8 [r31] = r37, -8 ;; /* save in5 */
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| 148 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */
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| 149 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */
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| 150 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */
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| 151 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */
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| 152 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */
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| 153 | (p5) add r31 = -56, r31 ;;
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| 154 |
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| 155 | st8 [r31] = r30, -8 ;; /* save old stack pointer */
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| 156 |
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| 157 | st8 [r31] = r29, -8 ;; /* save predicate registers */
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| 158 |
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| 159 | st8 [r31] = r24, -8 ;; /* save cr.iip */
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| 160 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */
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| 161 | st8 [r31] = r26, -8 ;; /* save cr.iipa */
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| 162 | st8 [r31] = r27, -8 ;; /* save cr.isr */
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| 163 | st8 [r31] = r28, -8 ;; /* save cr.ifa */
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| 164 |
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| 165 | /* 5. RSE switch from interrupted context */
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| 166 | mov r24 = ar.rsc
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| 167 | mov r25 = ar.pfs
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| 168 | cover
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| 169 | mov r26 = cr.ifs
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| 170 |
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| 171 | st8 [r31] = r24, -8 ;; /* save ar.rsc */
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| 172 | st8 [r31] = r25, -8 ;; /* save ar.pfs */
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| 173 | st8 [r31] = r26, -8 /* save ar.ifs */
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| 174 |
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| 175 | and r24 = ~(RSC_PL_MASK), r24 ;;
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| 176 | and r30 = ~(RSC_MODE_MASK), r24 ;;
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| 177 | mov ar.rsc = r30 ;; /* update RSE state */
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| 178 |
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| 179 | mov r27 = ar.rnat
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| 180 | mov r28 = ar.bspstore ;;
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| 181 |
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| 182 | /*
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| 183 | * Inspect BSPSTORE to figure out whether it is necessary to switch to
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| 184 | * kernel BSPSTORE.
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| 185 | */
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| 186 | (p1) shr.u r30 = r28, VRN_SHIFT ;;
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| 187 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
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| 188 |
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| 189 | /*
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| 190 | * If BSPSTORE needs to be switched, p1 is false and p2 is true.
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| 191 | */
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| 192 | (p1) mov r30 = r28
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| 193 | (p2) mov r30 = R_KSTACK_BSP ;;
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| 194 | (p2) mov ar.bspstore = r30 ;;
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| 195 |
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| 196 | mov r29 = ar.bsp
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| 197 |
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| 198 | st8 [r31] = r27, -8 ;; /* save ar.rnat */
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| 199 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */
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| 200 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */
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| 201 | st8 [r31] = r29, -8 /* save ar.bsp */
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| 202 |
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| 203 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
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| 204 |
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| 205 | /* steps 6 - 15 are done by heavyweight_handler_inner() */
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| 206 | mov R_RET = b0 /* save b0 belonging to interrupted context */
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| 207 | br.call.sptk.many b0 = heavyweight_handler_inner
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| 208 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
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| 209 |
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| 210 | /* 16. RSE switch to interrupted context */
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| 211 | cover /* allocate zero size frame (step 1 (from Intel Docs)) */
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| 212 |
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| 213 | add r31 = (STACK_SCRATCH_AREA_SIZE + (FRS_TO_SAVE * 2 * 8)), r12 ;;
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| 214 |
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| 215 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */
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| 216 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
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| 217 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
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| 218 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
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| 219 | shl r27 = r27, 16
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| 220 |
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| 221 | mov r24 = ar.rsc ;;
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| 222 | and r30 = ~3, r24 ;;
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| 223 | or r24 = r30 , r27 ;;
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| 224 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
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| 225 |
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| 226 | loadrs /* (step 3) */
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| 227 |
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| 228 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */
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| 229 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */
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| 230 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */
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| 231 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */
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| 232 |
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| 233 | mov ar.bspstore = r29 ;; /* (step 4) */
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| 234 | mov ar.rnat = r27 /* (step 5) */
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| 235 |
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| 236 | mov ar.pfs = r25 /* (step 6) */
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| 237 | mov cr.ifs = r26
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| 238 |
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| 239 | mov ar.rsc = r24 /* (step 7) */
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| 240 |
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| 241 | /* 17. restore interruption state from memory stack */
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| 242 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */
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| 243 | ld8 r27 = [r31], +8 ;; /* load cr.isr */
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| 244 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */
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| 245 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
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| 246 | ld8 r24 = [r31], +8 ;; /* load cr.iip */
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| 247 |
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| 248 | mov cr.iip = r24;;
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| 249 | mov cr.iipa = r26
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| 250 | mov cr.isr = r27
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| 251 | mov cr.ifa = r28
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| 252 |
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| 253 | /* Set up FPU as in exception. */
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| 254 | mov r24 = psr
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| 255 | mov r26 = PSR_DFH_MASK
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| 256 | mov r27 = ~PSR_DFH_MASK ;;
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| 257 | and r25 = r25, r27
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| 258 | and r24 = r24, r26 ;;
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| 259 | or r25 = r25, r24;;
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| 260 | mov cr.ipsr = r25
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| 261 |
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| 262 | /* 18. restore predicate registers from memory stack */
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| 263 | ld8 r29 = [r31], +8 ;; /* load predicate registers */
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| 264 | mov pr = r29
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| 265 |
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| 266 | /* 19. return from interruption */
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| 267 | ld8 r12 = [r31] /* load stack pointer */
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| 268 | rfi ;;
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| 269 |
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| 270 | .global heavyweight_handler_inner
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| 271 | heavyweight_handler_inner:
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| 272 | /*
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| 273 | * From this point, the rest of the interrupted context
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| 274 | * will be preserved in stacked registers and backing store.
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| 275 | */
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| 276 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
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| 277 |
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| 278 | /* bank 0 is going to be shadowed, copy essential data from there */
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| 279 | mov loc1 = R_RET /* b0 belonging to interrupted context */
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| 280 | mov loc2 = R_HANDLER
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| 281 | mov out0 = R_OFFS
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| 282 |
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| 283 | add out1 = STACK_SCRATCH_AREA_SIZE, r12
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| 284 |
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| 285 | /* 6. switch to bank 1 and reenable PSR.ic */
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| 286 | ssm PSR_IC_MASK
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| 287 | bsw.1 ;;
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| 288 | srlz.d
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| 289 |
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| 290 | /* 7. preserve branch and application registers */
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| 291 | mov loc3 = ar.unat
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| 292 | mov loc4 = ar.lc
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| 293 | mov loc5 = ar.ec
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| 294 | mov loc6 = ar.ccv
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| 295 | mov loc7 = ar.csd
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| 296 | mov loc8 = ar.ssd
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| 297 |
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| 298 | mov loc9 = b0
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| 299 | mov loc10 = b1
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| 300 | mov loc11 = b2
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| 301 | mov loc12 = b3
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| 302 | mov loc13 = b4
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| 303 | mov loc14 = b5
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| 304 | mov loc15 = b6
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| 305 | mov loc16 = b7
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| 306 |
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| 307 | /* 8. preserve general and floating-point registers */
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| 308 | mov loc17 = r1
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| 309 | mov loc18 = r2
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| 310 | mov loc19 = r3
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| 311 | mov loc20 = r4
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| 312 | mov loc21 = r5
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| 313 | mov loc22 = r6
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| 314 | mov loc23 = r7
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| 315 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */
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| 316 | mov loc25 = r9
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| 317 | mov loc26 = r10
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| 318 | mov loc27 = r11
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| 319 | /* skip r12 (stack pointer) */
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| 320 | mov loc28 = r13
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| 321 | mov loc29 = r14
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| 322 | mov loc30 = r15
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| 323 | mov loc31 = r16
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| 324 | mov loc32 = r17
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| 325 | mov loc33 = r18
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| 326 | mov loc34 = r19
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| 327 | mov loc35 = r20
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| 328 | mov loc36 = r21
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| 329 | mov loc37 = r22
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| 330 | mov loc38 = r23
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| 331 | mov loc39 = r24
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| 332 | mov loc40 = r25
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| 333 | mov loc41 = r26
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| 334 | mov loc42 = r27
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| 335 | mov loc43 = r28
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| 336 | mov loc44 = r29
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| 337 | mov loc45 = r30
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| 338 | mov loc46 = r31
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| 339 |
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| 340 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
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| 341 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
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| 342 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
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| 343 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
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| 344 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
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| 345 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
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| 346 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
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| 347 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
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| 348 |
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| 349 | stf.spill [r26] = f2, 0x80
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| 350 | stf.spill [r27] = f3, 0x80
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| 351 | stf.spill [r28] = f4, 0x80
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| 352 | stf.spill [r29] = f5, 0x80
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| 353 | stf.spill [r30] = f6, 0x80
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| 354 | stf.spill [r31] = f7, 0x80 ;;
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| 355 |
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| 356 | stf.spill [r24] = f8, 0x80
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| 357 | stf.spill [r25] = f9, 0x80
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| 358 | stf.spill [r26] = f10, 0x80
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| 359 | stf.spill [r27] = f11, 0x80
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| 360 | stf.spill [r28] = f12, 0x80
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| 361 | stf.spill [r29] = f13, 0x80
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| 362 | stf.spill [r30] = f14, 0x80
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| 363 | stf.spill [r31] = f15, 0x80 ;;
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| 364 |
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| 365 | stf.spill [r24] = f16, 0x80
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| 366 | stf.spill [r25] = f17, 0x80
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| 367 | stf.spill [r26] = f18, 0x80
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| 368 | stf.spill [r27] = f19, 0x80
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| 369 | stf.spill [r28] = f20, 0x80
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| 370 | stf.spill [r29] = f21, 0x80
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| 371 | stf.spill [r30] = f22, 0x80
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| 372 | stf.spill [r31] = f23, 0x80 ;;
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| 373 |
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| 374 | stf.spill [r24] = f24, 0x80
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| 375 | stf.spill [r25] = f25, 0x80
|
|---|
| 376 | stf.spill [r26] = f26, 0x80
|
|---|
| 377 | stf.spill [r27] = f27, 0x80
|
|---|
| 378 | stf.spill [r28] = f28, 0x80
|
|---|
| 379 | stf.spill [r29] = f29, 0x80
|
|---|
| 380 | stf.spill [r30] = f30, 0x80
|
|---|
| 381 | stf.spill [r31] = f31, 0x80 ;;
|
|---|
| 382 |
|
|---|
| 383 | mov loc47 = ar.fpsr /* preserve floating point status register */
|
|---|
| 384 |
|
|---|
| 385 | /* 9. skipped (will not enable interrupts) */
|
|---|
| 386 | /*
|
|---|
| 387 | * ssm PSR_I_MASK
|
|---|
| 388 | * ;;
|
|---|
| 389 | * srlz.d
|
|---|
| 390 | */
|
|---|
| 391 |
|
|---|
| 392 | /* 10. call handler */
|
|---|
| 393 | movl r1 = kernel_image_start
|
|---|
| 394 |
|
|---|
| 395 | mov b1 = loc2
|
|---|
| 396 | br.call.sptk.many b0 = b1
|
|---|
| 397 |
|
|---|
| 398 | /* 11. return from handler */
|
|---|
| 399 | 0:
|
|---|
| 400 |
|
|---|
| 401 | /* 12. skipped (will not disable interrupts) */
|
|---|
| 402 | /*
|
|---|
| 403 | * rsm PSR_I_MASK
|
|---|
| 404 | * ;;
|
|---|
| 405 | * srlz.d
|
|---|
| 406 | */
|
|---|
| 407 |
|
|---|
| 408 | /* 13. restore general and floating-point registers */
|
|---|
| 409 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 410 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 411 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 412 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 413 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 414 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 415 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
|
|---|
| 416 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
|
|---|
| 417 |
|
|---|
| 418 | ldf.fill f2 = [r26], 0x80
|
|---|
| 419 | ldf.fill f3 = [r27], 0x80
|
|---|
| 420 | ldf.fill f4 = [r28], 0x80
|
|---|
| 421 | ldf.fill f5 = [r29], 0x80
|
|---|
| 422 | ldf.fill f6 = [r30], 0x80
|
|---|
| 423 | ldf.fill f7 = [r31], 0x80 ;;
|
|---|
| 424 |
|
|---|
| 425 | ldf.fill f8 = [r24], 0x80
|
|---|
| 426 | ldf.fill f9 = [r25], 0x80
|
|---|
| 427 | ldf.fill f10 = [r26], 0x80
|
|---|
| 428 | ldf.fill f11 = [r27], 0x80
|
|---|
| 429 | ldf.fill f12 = [r28], 0x80
|
|---|
| 430 | ldf.fill f13 = [r29], 0x80
|
|---|
| 431 | ldf.fill f14 = [r30], 0x80
|
|---|
| 432 | ldf.fill f15 = [r31], 0x80 ;;
|
|---|
| 433 |
|
|---|
| 434 | ldf.fill f16 = [r24], 0x80
|
|---|
| 435 | ldf.fill f17 = [r25], 0x80
|
|---|
| 436 | ldf.fill f18 = [r26], 0x80
|
|---|
| 437 | ldf.fill f19 = [r27], 0x80
|
|---|
| 438 | ldf.fill f20 = [r28], 0x80
|
|---|
| 439 | ldf.fill f21 = [r29], 0x80
|
|---|
| 440 | ldf.fill f22 = [r30], 0x80
|
|---|
| 441 | ldf.fill f23 = [r31], 0x80 ;;
|
|---|
| 442 |
|
|---|
| 443 | ldf.fill f24 = [r24], 0x80
|
|---|
| 444 | ldf.fill f25 = [r25], 0x80
|
|---|
| 445 | ldf.fill f26 = [r26], 0x80
|
|---|
| 446 | ldf.fill f27 = [r27], 0x80
|
|---|
| 447 | ldf.fill f28 = [r28], 0x80
|
|---|
| 448 | ldf.fill f29 = [r29], 0x80
|
|---|
| 449 | ldf.fill f30 = [r30], 0x80
|
|---|
| 450 | ldf.fill f31 = [r31], 0x80 ;;
|
|---|
| 451 |
|
|---|
| 452 | mov r1 = loc17
|
|---|
| 453 | mov r2 = loc18
|
|---|
| 454 | mov r3 = loc19
|
|---|
| 455 | mov r4 = loc20
|
|---|
| 456 | mov r5 = loc21
|
|---|
| 457 | mov r6 = loc22
|
|---|
| 458 | mov r7 = loc23
|
|---|
| 459 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */
|
|---|
| 460 | mov r9 = loc25
|
|---|
| 461 | mov r10 = loc26
|
|---|
| 462 | mov r11 = loc27
|
|---|
| 463 | /* skip r12 (stack pointer) */
|
|---|
| 464 | mov r13 = loc28
|
|---|
| 465 | mov r14 = loc29
|
|---|
| 466 | mov r15 = loc30
|
|---|
| 467 | mov r16 = loc31
|
|---|
| 468 | mov r17 = loc32
|
|---|
| 469 | mov r18 = loc33
|
|---|
| 470 | mov r19 = loc34
|
|---|
| 471 | mov r20 = loc35
|
|---|
| 472 | mov r21 = loc36
|
|---|
| 473 | mov r22 = loc37
|
|---|
| 474 | mov r23 = loc38
|
|---|
| 475 | mov r24 = loc39
|
|---|
| 476 | mov r25 = loc40
|
|---|
| 477 | mov r26 = loc41
|
|---|
| 478 | mov r27 = loc42
|
|---|
| 479 | mov r28 = loc43
|
|---|
| 480 | mov r29 = loc44
|
|---|
| 481 | mov r30 = loc45
|
|---|
| 482 | mov r31 = loc46
|
|---|
| 483 |
|
|---|
| 484 | mov ar.fpsr = loc47 /* restore floating point status register */
|
|---|
| 485 |
|
|---|
| 486 | /* 14. restore branch and application registers */
|
|---|
| 487 | mov ar.unat = loc3
|
|---|
| 488 | mov ar.lc = loc4
|
|---|
| 489 | mov ar.ec = loc5
|
|---|
| 490 | mov ar.ccv = loc6
|
|---|
| 491 | mov ar.csd = loc7
|
|---|
| 492 | mov ar.ssd = loc8
|
|---|
| 493 |
|
|---|
| 494 | mov b0 = loc9
|
|---|
| 495 | mov b1 = loc10
|
|---|
| 496 | mov b2 = loc11
|
|---|
| 497 | mov b3 = loc12
|
|---|
| 498 | mov b4 = loc13
|
|---|
| 499 | mov b5 = loc14
|
|---|
| 500 | mov b6 = loc15
|
|---|
| 501 | mov b7 = loc16
|
|---|
| 502 |
|
|---|
| 503 | /* 15. disable PSR.ic and switch to bank 0 */
|
|---|
| 504 | rsm PSR_IC_MASK
|
|---|
| 505 | bsw.0 ;;
|
|---|
| 506 | srlz.d
|
|---|
| 507 |
|
|---|
| 508 | mov R_RET = loc1
|
|---|
| 509 | mov ar.pfs = loc0
|
|---|
| 510 | br.ret.sptk.many b0
|
|---|
| 511 |
|
|---|
| 512 | .global ivt
|
|---|
| 513 | .align 32768
|
|---|
| 514 | ivt:
|
|---|
| 515 | HEAVYWEIGHT_HANDLER 0x0000
|
|---|
| 516 | HEAVYWEIGHT_HANDLER 0x0400
|
|---|
| 517 | HEAVYWEIGHT_HANDLER 0x0800
|
|---|
| 518 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
|
|---|
| 519 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
|
|---|
| 520 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
|
|---|
| 521 | HEAVYWEIGHT_HANDLER 0x1800
|
|---|
| 522 | HEAVYWEIGHT_HANDLER 0x1c00
|
|---|
| 523 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
|
|---|
| 524 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
|
|---|
| 525 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
|
|---|
| 526 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
|
|---|
| 527 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
|
|---|
| 528 | HEAVYWEIGHT_HANDLER 0x3400
|
|---|
| 529 | HEAVYWEIGHT_HANDLER 0x3800
|
|---|
| 530 | HEAVYWEIGHT_HANDLER 0x3c00
|
|---|
| 531 | HEAVYWEIGHT_HANDLER 0x4000
|
|---|
| 532 | HEAVYWEIGHT_HANDLER 0x4400
|
|---|
| 533 | HEAVYWEIGHT_HANDLER 0x4800
|
|---|
| 534 | HEAVYWEIGHT_HANDLER 0x4c00
|
|---|
| 535 |
|
|---|
| 536 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present
|
|---|
| 537 | HEAVYWEIGHT_HANDLER 0x5100
|
|---|
| 538 | HEAVYWEIGHT_HANDLER 0x5200
|
|---|
| 539 | HEAVYWEIGHT_HANDLER 0x5300 data_access_rights_fault
|
|---|
| 540 | HEAVYWEIGHT_HANDLER 0x5400 general_exception
|
|---|
| 541 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
|
|---|
| 542 | HEAVYWEIGHT_HANDLER 0x5600
|
|---|
| 543 | HEAVYWEIGHT_HANDLER 0x5700
|
|---|
| 544 | HEAVYWEIGHT_HANDLER 0x5800
|
|---|
| 545 | HEAVYWEIGHT_HANDLER 0x5900
|
|---|
| 546 | HEAVYWEIGHT_HANDLER 0x5a00
|
|---|
| 547 | HEAVYWEIGHT_HANDLER 0x5b00
|
|---|
| 548 | HEAVYWEIGHT_HANDLER 0x5c00
|
|---|
| 549 | HEAVYWEIGHT_HANDLER 0x5d00
|
|---|
| 550 | HEAVYWEIGHT_HANDLER 0x5e00
|
|---|
| 551 | HEAVYWEIGHT_HANDLER 0x5f00
|
|---|
| 552 |
|
|---|
| 553 | HEAVYWEIGHT_HANDLER 0x6000
|
|---|
| 554 | HEAVYWEIGHT_HANDLER 0x6100
|
|---|
| 555 | HEAVYWEIGHT_HANDLER 0x6200
|
|---|
| 556 | HEAVYWEIGHT_HANDLER 0x6300
|
|---|
| 557 | HEAVYWEIGHT_HANDLER 0x6400
|
|---|
| 558 | HEAVYWEIGHT_HANDLER 0x6500
|
|---|
| 559 | HEAVYWEIGHT_HANDLER 0x6600
|
|---|
| 560 | HEAVYWEIGHT_HANDLER 0x6700
|
|---|
| 561 | HEAVYWEIGHT_HANDLER 0x6800
|
|---|
| 562 | HEAVYWEIGHT_HANDLER 0x6900
|
|---|
| 563 | HEAVYWEIGHT_HANDLER 0x6a00
|
|---|
| 564 | HEAVYWEIGHT_HANDLER 0x6b00
|
|---|
| 565 | HEAVYWEIGHT_HANDLER 0x6c00
|
|---|
| 566 | HEAVYWEIGHT_HANDLER 0x6d00
|
|---|
| 567 | HEAVYWEIGHT_HANDLER 0x6e00
|
|---|
| 568 | HEAVYWEIGHT_HANDLER 0x6f00
|
|---|
| 569 |
|
|---|
| 570 | HEAVYWEIGHT_HANDLER 0x7000
|
|---|
| 571 | HEAVYWEIGHT_HANDLER 0x7100
|
|---|
| 572 | HEAVYWEIGHT_HANDLER 0x7200
|
|---|
| 573 | HEAVYWEIGHT_HANDLER 0x7300
|
|---|
| 574 | HEAVYWEIGHT_HANDLER 0x7400
|
|---|
| 575 | HEAVYWEIGHT_HANDLER 0x7500
|
|---|
| 576 | HEAVYWEIGHT_HANDLER 0x7600
|
|---|
| 577 | HEAVYWEIGHT_HANDLER 0x7700
|
|---|
| 578 | HEAVYWEIGHT_HANDLER 0x7800
|
|---|
| 579 | HEAVYWEIGHT_HANDLER 0x7900
|
|---|
| 580 | HEAVYWEIGHT_HANDLER 0x7a00
|
|---|
| 581 | HEAVYWEIGHT_HANDLER 0x7b00
|
|---|
| 582 | HEAVYWEIGHT_HANDLER 0x7c00
|
|---|
| 583 | HEAVYWEIGHT_HANDLER 0x7d00
|
|---|
| 584 | HEAVYWEIGHT_HANDLER 0x7e00
|
|---|
| 585 | HEAVYWEIGHT_HANDLER 0x7f00
|
|---|
