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Last change on this file since 49319ac was 11675207, checked in by jermar <jermar@…>, 17 years ago
Move everything to kernel/.
Property mode set to `100644`
File size: 15.5 KB

Rev	Line
[d2bb9f8a]	1	#
	2	# Copyright (C) 2005 Jakub Vana
[8a0b3730]	3	# Copyright (C) 2005 Jakub Jermar
[d2bb9f8a]	4	# All rights reserved.
	5	#
	6	# Redistribution and use in source and binary forms, with or without
	7	# modification, are permitted provided that the following conditions
	8	# are met:
	9	#
	10	# - Redistributions of source code must retain the above copyright
	11	# notice, this list of conditions and the following disclaimer.
	12	# - Redistributions in binary form must reproduce the above copyright
	13	# notice, this list of conditions and the following disclaimer in the
	14	# documentation and/or other materials provided with the distribution.
	15	# - The name of the author may not be used to endorse or promote products
	16	# derived from this software without specific prior written permission.
	17	#
	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	#
	29
[17a20bc]	30	#include <arch/stack.h>
[8a0b3730]	31	#include <arch/register.h>
[83d2d0e]	32	#include <arch/mm/page.h>
	33	#include <align.h>
[17a20bc]	34
[41fa6f2]	35	#define FRS_TO_SAVE 30
	36	#define STACK_ITEMS (19 + FRS_TO_SAVE*2)
[83d2d0e]	37	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
[17a20bc]	38
[83d2d0e]	39	#if (STACK_ITEMS % 2 == 0)
	40	# define STACK_FRAME_BIAS 8
	41	#else
	42	# define STACK_FRAME_BIAS 16
[17a20bc]	43	#endif
[d2bb9f8a]	44
[bc314be8]	45	/** Partitioning of bank 0 registers. */
	46	#define R_OFFS r16
	47	#define R_HANDLER r17
	48	#define R_RET r18
[901122b]	49	#define R_TMP r19
[cd373bb]	50	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
[bc314be8]	51	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
	52
[2262044]	53	/** Heavyweight interrupt handler
	54	*
[154049e]	55	* This macro roughly follows steps from 1 to 19 described in
	56	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
	57	*
[2262044]	58	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
	59	* This goal is achieved by using procedure calls after RSE becomes operational.
	60	*
[154049e]	61	* Some steps are skipped (enabling and disabling interrupts).
[5b65205]	62	*
	63	* @param offs Offset from the beginning of IVT.
	64	* @param handler Interrupt handler address.
[154049e]	65	*/
[e2ec980f]	66	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
	67	.org ivt + \offs
[bc314be8]	68	mov R_OFFS = \offs
	69	movl R_HANDLER = \handler ;;
[e2ec980f]	70	br heavyweight_handler
	71	.endm
[154049e]	72
[e2ec980f]	73	.global heavyweight_handler
	74	heavyweight_handler:
[154049e]	75	/* 1. copy interrupt registers into bank 0 */
[bc314be8]	76
	77	/*
[83d2d0e]	78	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
[bc314be8]	79	*/
[41fa6f2]	80
[2ba1f39]	81	/* Set up FPU as in interrupted context. */
	82	mov r24 = psr
	83	mov r25 = cr.ipsr
	84	mov r26 = PSR_DFH_MASK
	85	mov r27 = ~PSR_DFH_MASK ;;
	86	and r26 = r25, r26
	87	and r24 = r24, r27;;
	88	or r24 = r24, r26;;
	89	mov psr.l = r24;;
[41fa6f2]	90	srlz.i
	91	srlz.d;;
	92
[154049e]	93	mov r24 = cr.iip
	94	mov r25 = cr.ipsr
	95	mov r26 = cr.iipa
	96	mov r27 = cr.isr
	97	mov r28 = cr.ifa
	98
	99	/* 2. preserve predicate register into bank 0 */
	100	mov r29 = pr ;;
	101
[2262044]	102	/* 3. switch to kernel memory stack */
[83d2d0e]	103	mov r30 = cr.ipsr
[cd373bb]	104	shr.u r31 = r12, VRN_SHIFT ;;
	105
	106	shr.u r30 = r30, PSR_CPL_SHIFT ;;
	107	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
[83d2d0e]	108
	109	/*
[cd373bb]	110	* Set p3 to true if the interrupted context executed in kernel mode.
	111	* Set p4 to false if the interrupted context didn't execute in kernel mode.
[83d2d0e]	112	*/
[cd373bb]	113	cmp.eq p3, p4 = r30, r0 ;;
	114	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
[83d2d0e]	115
	116	/*
[cd373bb]	117	* Set p3 to true if the stack register references kernel address space.
	118	* Set p4 to false if the stack register doesn't reference kernel address space.
[83d2d0e]	119	*/
[901122b]	120	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
[83d2d0e]	121
	122	/*
[cd373bb]	123	* Now, p4 is true iff the stack needs to be switched to kernel stack.
[83d2d0e]	124	*/
	125	mov r30 = r12
[901122b]	126	(p4) mov r12 = R_KSTACK ;;
[83d2d0e]	127
	128	add r31 = -STACK_FRAME_BIAS, r12 ;;
[e2ec980f]	129	add r12 = -STACK_FRAME_SIZE, r12
	130
[901122b]	131	/* 4. save registers in bank 0 into memory stack */
	132
	133	/*
	134	* If this is break_instruction handler,
	135	* copy input parameters to stack.
	136	*/
	137	mov R_TMP = 0x2c00 ;;
	138	cmp.eq p6,p5 = R_OFFS, R_TMP ;;
	139
	140	/*
	141	* From now on, if this is break_instruction handler, p6 is true and p5 is false.
	142	* Otherwise p6 is false and p5 is true.
	143	* Note that p5 is a preserved predicate register and we make use of it.
	144	*/
[5c089c3a]	145
	146	(p6) st8 [r31] = r36, -8 ;; /* save in4 */
[901122b]	147	(p6) st8 [r31] = r35, -8 ;; /* save in3 */
	148	(p6) st8 [r31] = r34, -8 ;; /* save in2 */
	149	(p6) st8 [r31] = r33, -8 ;; /* save in1 */
	150	(p6) st8 [r31] = r32, -8 ;; /* save in0 */
[5c089c3a]	151	(p5) add r31 = -40, r31 ;;
[901122b]	152
[83d2d0e]	153	st8 [r31] = r30, -8 ;; /* save old stack pointer */
	154
	155	st8 [r31] = r29, -8 ;; /* save predicate registers */
[2262044]	156
[83d2d0e]	157	st8 [r31] = r24, -8 ;; /* save cr.iip */
	158	st8 [r31] = r25, -8 ;; /* save cr.ipsr */
	159	st8 [r31] = r26, -8 ;; /* save cr.iipa */
	160	st8 [r31] = r27, -8 ;; /* save cr.isr */
	161	st8 [r31] = r28, -8 ;; /* save cr.ifa */
[2262044]	162
	163	/* 5. RSE switch from interrupted context */
[154049e]	164	mov r24 = ar.rsc
	165	mov r25 = ar.pfs
	166	cover
	167	mov r26 = cr.ifs
	168
[cd373bb]	169	st8 [r31] = r24, -8 ;; /* save ar.rsc */
	170	st8 [r31] = r25, -8 ;; /* save ar.pfs */
	171	st8 [r31] = r26, -8 /* save ar.ifs */
[154049e]	172
[b994a60]	173	and r24 = ~(RSC_PL_MASK), r24 ;;
	174	and r30 = ~(RSC_MODE_MASK), r24 ;;
	175	mov ar.rsc = r30 ;; /* update RSE state */
[154049e]	176
	177	mov r27 = ar.rnat
[e2ec980f]	178	mov r28 = ar.bspstore ;;
[154049e]	179
[cd373bb]	180	/*
	181	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
	182	*/
[901122b]	183	(p1) shr.u r30 = r28, VRN_SHIFT ;;
	184	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
[cd373bb]	185
	186	/*
	187	* If BSPSTORE needs to be switched, p1 is false and p2 is true.
	188	*/
[901122b]	189	(p1) mov r30 = r28
	190	(p2) mov r30 = R_KSTACK_BSP ;;
	191	(p2) mov ar.bspstore = r30 ;;
[154049e]	192
	193	mov r29 = ar.bsp
	194
[cd373bb]	195	st8 [r31] = r27, -8 ;; /* save ar.rnat */
	196	st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */
	197	st8 [r31] = r28, -8 ;; /* save ar.bspstore */
	198	st8 [r31] = r29, -8 /* save ar.bsp */
[154049e]	199
[b994a60]	200	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
[154049e]	201
[e2ec980f]	202	/* steps 6 - 15 are done by heavyweight_handler_inner() */
[cd373bb]	203	mov R_RET = b0 /* save b0 belonging to interrupted context */
[bc314be8]	204	br.call.sptk.many b0 = heavyweight_handler_inner
[cd373bb]	205	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
[2262044]	206
[e2ec980f]	207	/* 16. RSE switch to interrupted context */
[cd373bb]	208	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
[e2ec980f]	209
[41fa6f2]	210	add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE28)), r12 ;;
[e2ec980f]	211
[e1c68e0c]	212	ld8 r30 = [r31], +8 ;; /* load ar.bsp */
	213	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
	214	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
	215	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
[e2ec980f]	216	shl r27 = r27, 16
	217
	218	mov r24 = ar.rsc ;;
	219	and r30 = ~3, r24 ;;
	220	or r24 = r30 , r27 ;;
	221	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
	222
	223	loadrs /* (step 3) */
	224
	225	ld8 r27 = [r31], +8 ;; /* load ar.rnat */
	226	ld8 r26 = [r31], +8 ;; /* load cr.ifs */
	227	ld8 r25 = [r31], +8 ;; /* load ar.pfs */
	228	ld8 r24 = [r31], +8 ;; /* load ar.rsc */
	229
[e1c68e0c]	230	mov ar.bspstore = r29 ;; /* (step 4) */
	231	mov ar.rnat = r27 /* (step 5) */
[e2ec980f]	232
	233	mov ar.pfs = r25 /* (step 6) */
	234	mov cr.ifs = r26
	235
	236	mov ar.rsc = r24 /* (step 7) */
	237
	238	/* 17. restore interruption state from memory stack */
[cd373bb]	239	ld8 r28 = [r31], +8 ;; /* load cr.ifa */
	240	ld8 r27 = [r31], +8 ;; /* load cr.isr */
	241	ld8 r26 = [r31], +8 ;; /* load cr.iipa */
	242	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
	243	ld8 r24 = [r31], +8 ;; /* load cr.iip */
[e2ec980f]	244
[41fa6f2]	245	mov cr.iip = r24;;
[e2ec980f]	246	mov cr.iipa = r26
	247	mov cr.isr = r27
	248	mov cr.ifa = r28
[2ba1f39]	249
	250	/* Set up FPU as in exception. */
	251	mov r24 = psr
	252	mov r26 = PSR_DFH_MASK
	253	mov r27 = ~PSR_DFH_MASK ;;
	254	and r25 = r25, r27
	255	and r24 = r24, r26 ;;
	256	or r25 = r25, r24;;
[41fa6f2]	257	mov cr.ipsr = r25
[e2ec980f]	258
	259	/* 18. restore predicate registers from memory stack */
[cd373bb]	260	ld8 r29 = [r31], +8 ;; /* load predicate registers */
[e2ec980f]	261	mov pr = r29
	262
	263	/* 19. return from interruption */
[cd373bb]	264	ld8 r12 = [r31] /* load stack pointer */
[e2ec980f]	265	rfi ;;
[2262044]	266
	267	.global heavyweight_handler_inner
	268	heavyweight_handler_inner:
	269	/*
	270	* From this point, the rest of the interrupted context
	271	* will be preserved in stacked registers and backing store.
	272	*/
[5581c45e]	273	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
[2262044]	274
[e2ec980f]	275	/* bank 0 is going to be shadowed, copy essential data from there */
[bc314be8]	276	mov loc1 = R_RET /* b0 belonging to interrupted context */
	277	mov loc2 = R_HANDLER
	278	mov out0 = R_OFFS
[e2ec980f]	279
	280	add out1 = STACK_SCRATCH_AREA_SIZE, r12
[2262044]	281
[154049e]	282	/* 6. switch to bank 1 and reenable PSR.ic */
[8a0b3730]	283	ssm PSR_IC_MASK
[154049e]	284	bsw.1 ;;
	285	srlz.d
	286
	287	/* 7. preserve branch and application registers */
[e2ec980f]	288	mov loc3 = ar.unat
	289	mov loc4 = ar.lc
	290	mov loc5 = ar.ec
	291	mov loc6 = ar.ccv
	292	mov loc7 = ar.csd
	293	mov loc8 = ar.ssd
[2262044]	294
[e2ec980f]	295	mov loc9 = b0
	296	mov loc10 = b1
	297	mov loc11 = b2
	298	mov loc12 = b3
	299	mov loc13 = b4
	300	mov loc14 = b5
	301	mov loc15 = b6
	302	mov loc16 = b7
[154049e]	303
	304	/* 8. preserve general and floating-point registers */
[e2ec980f]	305	mov loc17 = r1
	306	mov loc18 = r2
	307	mov loc19 = r3
	308	mov loc20 = r4
	309	mov loc21 = r5
	310	mov loc22 = r6
	311	mov loc23 = r7
[901122b]	312	(p5) mov loc24 = r8 /* only if not in break_instruction handler */
[e2ec980f]	313	mov loc25 = r9
	314	mov loc26 = r10
	315	mov loc27 = r11
[2262044]	316	/* skip r12 (stack pointer) */
[e2ec980f]	317	mov loc28 = r13
	318	mov loc29 = r14
	319	mov loc30 = r15
	320	mov loc31 = r16
	321	mov loc32 = r17
	322	mov loc33 = r18
	323	mov loc34 = r19
	324	mov loc35 = r20
	325	mov loc36 = r21
	326	mov loc37 = r22
	327	mov loc38 = r23
	328	mov loc39 = r24
	329	mov loc40 = r25
	330	mov loc41 = r26
	331	mov loc42 = r27
	332	mov loc43 = r28
	333	mov loc44 = r29
	334	mov loc45 = r30
	335	mov loc46 = r31
[5581c45e]	336
[2ba1f39]	337	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
	338	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
	339	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
	340	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
	341	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
	342	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
	343	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
	344	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
	345
	346	stf.spill [r26] = f2, 0x80
	347	stf.spill [r27] = f3, 0x80
	348	stf.spill [r28] = f4, 0x80
	349	stf.spill [r29] = f5, 0x80
	350	stf.spill [r30] = f6, 0x80
	351	stf.spill [r31] = f7, 0x80 ;;
	352
	353	stf.spill [r24] = f8, 0x80
	354	stf.spill [r25] = f9, 0x80
	355	stf.spill [r26] = f10, 0x80
	356	stf.spill [r27] = f11, 0x80
	357	stf.spill [r28] = f12, 0x80
	358	stf.spill [r29] = f13, 0x80
	359	stf.spill [r30] = f14, 0x80
	360	stf.spill [r31] = f15, 0x80 ;;
	361
	362	stf.spill [r24] = f16, 0x80
	363	stf.spill [r25] = f17, 0x80
	364	stf.spill [r26] = f18, 0x80
	365	stf.spill [r27] = f19, 0x80
	366	stf.spill [r28] = f20, 0x80
	367	stf.spill [r29] = f21, 0x80
	368	stf.spill [r30] = f22, 0x80
	369	stf.spill [r31] = f23, 0x80 ;;
	370
	371	stf.spill [r24] = f24, 0x80
	372	stf.spill [r25] = f25, 0x80
	373	stf.spill [r26] = f26, 0x80
	374	stf.spill [r27] = f27, 0x80
	375	stf.spill [r28] = f28, 0x80
	376	stf.spill [r29] = f29, 0x80
	377	stf.spill [r30] = f30, 0x80
	378	stf.spill [r31] = f31, 0x80 ;;
	379
	380	mov loc47 = ar.fpsr /* preserve floating point status register */
[2262044]	381
[154049e]	382	/* 9. skipped (will not enable interrupts) */
[8a0b3730]	383	/*
	384	* ssm PSR_I_MASK
	385	* ;;
	386	* srlz.d
	387	*/
[154049e]	388
[2262044]	389	/* 10. call handler */
[b994a60]	390	movl r1 = _hardcoded_load_address
	391
[e2ec980f]	392	mov b1 = loc2
[2262044]	393	br.call.sptk.many b0 = b1
	394
	395	/* 11. return from handler */
	396	0:
[154049e]	397
[2262044]	398	/* 12. skipped (will not disable interrupts) */
[8a0b3730]	399	/*
	400	* rsm PSR_I_MASK
	401	* ;;
	402	* srlz.d
	403	*/
[2262044]	404
[154049e]	405	/* 13. restore general and floating-point registers */
[2ba1f39]	406	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
	407	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
	408	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
	409	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
	410	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
	411	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
	412	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
	413	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
	414
	415	ldf.fill f2 = [r26], 0x80
	416	ldf.fill f3 = [r27], 0x80
	417	ldf.fill f4 = [r28], 0x80
	418	ldf.fill f5 = [r29], 0x80
	419	ldf.fill f6 = [r30], 0x80
	420	ldf.fill f7 = [r31], 0x80 ;;
	421
	422	ldf.fill f8 = [r24], 0x80
	423	ldf.fill f9 = [r25], 0x80
	424	ldf.fill f10 = [r26], 0x80
	425	ldf.fill f11 = [r27], 0x80
	426	ldf.fill f12 = [r28], 0x80
	427	ldf.fill f13 = [r29], 0x80
	428	ldf.fill f14 = [r30], 0x80
	429	ldf.fill f15 = [r31], 0x80 ;;
	430
	431	ldf.fill f16 = [r24], 0x80
	432	ldf.fill f17 = [r25], 0x80
	433	ldf.fill f18 = [r26], 0x80
	434	ldf.fill f19 = [r27], 0x80
	435	ldf.fill f20 = [r28], 0x80
	436	ldf.fill f21 = [r29], 0x80
	437	ldf.fill f22 = [r30], 0x80
	438	ldf.fill f23 = [r31], 0x80 ;;
	439
	440	ldf.fill f24 = [r24], 0x80
	441	ldf.fill f25 = [r25], 0x80
	442	ldf.fill f26 = [r26], 0x80
	443	ldf.fill f27 = [r27], 0x80
	444	ldf.fill f28 = [r28], 0x80
	445	ldf.fill f29 = [r29], 0x80
	446	ldf.fill f30 = [r30], 0x80
	447	ldf.fill f31 = [r31], 0x80 ;;
[41fa6f2]	448
[e2ec980f]	449	mov r1 = loc17
	450	mov r2 = loc18
	451	mov r3 = loc19
	452	mov r4 = loc20
	453	mov r5 = loc21
	454	mov r6 = loc22
	455	mov r7 = loc23
[901122b]	456	(p5) mov r8 = loc24 /* only if not in break_instruction handler */
[e2ec980f]	457	mov r9 = loc25
	458	mov r10 = loc26
	459	mov r11 = loc27
[2262044]	460	/* skip r12 (stack pointer) */
[e2ec980f]	461	mov r13 = loc28
	462	mov r14 = loc29
	463	mov r15 = loc30
	464	mov r16 = loc31
	465	mov r17 = loc32
	466	mov r18 = loc33
	467	mov r19 = loc34
	468	mov r20 = loc35
	469	mov r21 = loc36
	470	mov r22 = loc37
	471	mov r23 = loc38
	472	mov r24 = loc39
	473	mov r25 = loc40
	474	mov r26 = loc41
	475	mov r27 = loc42
	476	mov r28 = loc43
	477	mov r29 = loc44
	478	mov r30 = loc45
	479	mov r31 = loc46
[2ba1f39]	480
	481	mov ar.fpsr = loc47 /* restore floating point status register */
[5581c45e]	482
[154049e]	483	/* 14. restore branch and application registers */
[e2ec980f]	484	mov ar.unat = loc3
	485	mov ar.lc = loc4
	486	mov ar.ec = loc5
	487	mov ar.ccv = loc6
	488	mov ar.csd = loc7
	489	mov ar.ssd = loc8
[2262044]	490
[e2ec980f]	491	mov b0 = loc9
	492	mov b1 = loc10
	493	mov b2 = loc11
	494	mov b3 = loc12
	495	mov b4 = loc13
	496	mov b5 = loc14
	497	mov b6 = loc15
	498	mov b7 = loc16
[154049e]	499
	500	/* 15. disable PSR.ic and switch to bank 0 */
[8a0b3730]	501	rsm PSR_IC_MASK
[154049e]	502	bsw.0 ;;
	503	srlz.d
[2262044]	504
[bc314be8]	505	mov R_RET = loc1
[2262044]	506	mov ar.pfs = loc0
[e2ec980f]	507	br.ret.sptk.many b0
[d2bb9f8a]	508
[e2ec980f]	509	.global ivt
[d2bb9f8a]	510	.align 32768
[e2ec980f]	511	ivt:
	512	HEAVYWEIGHT_HANDLER 0x0000
	513	HEAVYWEIGHT_HANDLER 0x0400
	514	HEAVYWEIGHT_HANDLER 0x0800
[95042fd]	515	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
	516	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
	517	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
[e2ec980f]	518	HEAVYWEIGHT_HANDLER 0x1800
	519	HEAVYWEIGHT_HANDLER 0x1c00
[95042fd]	520	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
	521	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
	522	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
[e2ec980f]	523	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
	524	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
	525	HEAVYWEIGHT_HANDLER 0x3400
	526	HEAVYWEIGHT_HANDLER 0x3800
	527	HEAVYWEIGHT_HANDLER 0x3c00
	528	HEAVYWEIGHT_HANDLER 0x4000
	529	HEAVYWEIGHT_HANDLER 0x4400
	530	HEAVYWEIGHT_HANDLER 0x4800
	531	HEAVYWEIGHT_HANDLER 0x4c00
	532
[95042fd]	533	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
[e2ec980f]	534	HEAVYWEIGHT_HANDLER 0x5100
	535	HEAVYWEIGHT_HANDLER 0x5200
	536	HEAVYWEIGHT_HANDLER 0x5300
	537	HEAVYWEIGHT_HANDLER 0x5400 general_exception
[9e1c942]	538	HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
[e2ec980f]	539	HEAVYWEIGHT_HANDLER 0x5600
	540	HEAVYWEIGHT_HANDLER 0x5700
	541	HEAVYWEIGHT_HANDLER 0x5800
	542	HEAVYWEIGHT_HANDLER 0x5900
	543	HEAVYWEIGHT_HANDLER 0x5a00
	544	HEAVYWEIGHT_HANDLER 0x5b00
	545	HEAVYWEIGHT_HANDLER 0x5c00
[9e1c942]	546	HEAVYWEIGHT_HANDLER 0x5d00
[e2ec980f]	547	HEAVYWEIGHT_HANDLER 0x5e00
	548	HEAVYWEIGHT_HANDLER 0x5f00
	549
	550	HEAVYWEIGHT_HANDLER 0x6000
	551	HEAVYWEIGHT_HANDLER 0x6100
	552	HEAVYWEIGHT_HANDLER 0x6200
	553	HEAVYWEIGHT_HANDLER 0x6300
	554	HEAVYWEIGHT_HANDLER 0x6400
	555	HEAVYWEIGHT_HANDLER 0x6500
	556	HEAVYWEIGHT_HANDLER 0x6600
	557	HEAVYWEIGHT_HANDLER 0x6700
	558	HEAVYWEIGHT_HANDLER 0x6800
	559	HEAVYWEIGHT_HANDLER 0x6900
	560	HEAVYWEIGHT_HANDLER 0x6a00
	561	HEAVYWEIGHT_HANDLER 0x6b00
	562	HEAVYWEIGHT_HANDLER 0x6c00
	563	HEAVYWEIGHT_HANDLER 0x6d00
	564	HEAVYWEIGHT_HANDLER 0x6e00
	565	HEAVYWEIGHT_HANDLER 0x6f00
	566
	567	HEAVYWEIGHT_HANDLER 0x7000
	568	HEAVYWEIGHT_HANDLER 0x7100
	569	HEAVYWEIGHT_HANDLER 0x7200
	570	HEAVYWEIGHT_HANDLER 0x7300
	571	HEAVYWEIGHT_HANDLER 0x7400
	572	HEAVYWEIGHT_HANDLER 0x7500
	573	HEAVYWEIGHT_HANDLER 0x7600
	574	HEAVYWEIGHT_HANDLER 0x7700
	575	HEAVYWEIGHT_HANDLER 0x7800
	576	HEAVYWEIGHT_HANDLER 0x7900
	577	HEAVYWEIGHT_HANDLER 0x7a00
	578	HEAVYWEIGHT_HANDLER 0x7b00
	579	HEAVYWEIGHT_HANDLER 0x7c00
	580	HEAVYWEIGHT_HANDLER 0x7d00
	581	HEAVYWEIGHT_HANDLER 0x7e00
	582	HEAVYWEIGHT_HANDLER 0x7f00

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