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Last change on this file was 70259a55, checked in by Jakub Jermar <jakub@…>, 7 years ago

ia64: Use appropriate imm21 operand with BREAK

This commit changes the imm21 used with the BREAK instruction to conform
to the IA-64 Software Conventions and Runtime Architecture Guide. This
is necessary to be able to distinguish syscalls from compiler-generated
calls to architected software interrupts (e.g. integer divide by zero).

In order to be able to test the used immediate in break_instruction(),
we extend istate_t to hold the CR.IIM register.

Property mode set to 100644

File size: 17.3 KB

Rev	Line
[d2bb9f8a]	1	#
[df4ed85]	2	# Copyright (c) 2005 Jakub Vana
	3	# Copyright (c) 2005 Jakub Jermar
[d2bb9f8a]	4	# All rights reserved.
	5	#
	6	# Redistribution and use in source and binary forms, with or without
	7	# modification, are permitted provided that the following conditions
	8	# are met:
	9	#
	10	# - Redistributions of source code must retain the above copyright
	11	# notice, this list of conditions and the following disclaimer.
	12	# - Redistributions in binary form must reproduce the above copyright
	13	# notice, this list of conditions and the following disclaimer in the
	14	# documentation and/or other materials provided with the distribution.
	15	# - The name of the author may not be used to endorse or promote products
	16	# derived from this software without specific prior written permission.
	17	#
	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	#
	29
[27f67f5]	30	#include <abi/asmtool.h>
[17a20bc]	31	#include <arch/stack.h>
[8a0b3730]	32	#include <arch/register.h>
[83d2d0e]	33	#include <arch/mm/page.h>
[9928240]	34	#include <arch/interrupt.h>
[293703e]	35	#include <arch/istate_struct.h>
[83d2d0e]	36	#include <align.h>
[17a20bc]	37
[293703e]	38	#define STACK_FRAME_SIZE ALIGN_UP(ISTATE_SIZE + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
[17a20bc]	39
[293703e]	40	#define FLOAT_ITEM_SIZE (STACK_ITEM_SIZE * 2)
[d2bb9f8a]	41
[bc314be8]	42	/** Partitioning of bank 0 registers. */
[9928240]	43	#define R_VECTOR r16
[bc314be8]	44	#define R_HANDLER r17
	45	#define R_RET r18
[cd373bb]	46	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
[bc314be8]	47	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
	48
[7b712b60]	49	/* Speculation vector handler */
[1b20da0]	50	.macro SPECULATION_VECTOR_HANDLER vector
[9928240]	51	.org ivt + \vector * 0x100
[7b712b60]	52
	53	/* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
	54	mov r16 = pr
	55	mov r17 = cr.iim
	56	mov r18 = cr.iip
	57	mov r19 = cr.ipsr
	58	mov r20 = cr.isr ;;
[a35b458]	59
[7b712b60]	60	/* 2. Move IIP to IIPA. */
	61	mov cr.iipa = r18
[a35b458]	62
[7b712b60]	63	/* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
	64	shl r17 = r17, 43 ;; /* shift bit 20 to bit 63 */
	65	shr r17 = r17, 39 ;; /* signed shift right to bit 24 */
	66	add r18 = r18, r17 ;;
	67	mov cr.iip = r18
[a35b458]	68
[7b712b60]	69	/* 4. Set IPSR.ri to 0. */
	70	dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
	71	mov cr.ipsr = r19
[a35b458]	72
[7b712b60]	73	/* 5. Check whether IPSR.tb or IPSR.ss is set. */
	74
	75	/* TODO:
	76	* Implement this when Taken Branch and Single Step traps can occur.
	77	*/
[a35b458]	78
[7b712b60]	79	/* 6. Restore predicates and return from interruption. */
	80	mov pr = r16 ;;
	81	rfi
	82	.endm
	83
[2262044]	84	/** Heavyweight interrupt handler
	85	*
[154049e]	86	* This macro roughly follows steps from 1 to 19 described in
	87	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
	88	*
[2262044]	89	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
	90	* This goal is achieved by using procedure calls after RSE becomes operational.
	91	*
[154049e]	92	* Some steps are skipped (enabling and disabling interrupts).
[5b65205]	93	*
	94	* @param offs Offset from the beginning of IVT.
	95	* @param handler Interrupt handler address.
[154049e]	96	*/
[9928240]	97	.macro HEAVYWEIGHT_HANDLER vector, handler=exc_dispatch
	98	.org ivt + \vector * 0x100
	99	mov R_VECTOR = \vector
[bc314be8]	100	movl R_HANDLER = \handler ;;
[e2ec980f]	101	br heavyweight_handler
	102	.endm
[154049e]	103
[27f67f5]	104	SYMBOL(heavyweight_handler)
[154049e]	105	/* 1. copy interrupt registers into bank 0 */
[a35b458]	106
[bc314be8]	107	/*
[83d2d0e]	108	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
[bc314be8]	109	*/
[a35b458]	110
[2ba1f39]	111	/* Set up FPU as in interrupted context. */
	112	mov r24 = psr
[1b20da0]	113	mov r25 = cr.ipsr
[2ba1f39]	114	mov r26 = PSR_DFH_MASK
	115	mov r27 = ~PSR_DFH_MASK ;;
	116	and r26 = r25, r26
[293703e]	117	and r24 = r24, r27 ;;
	118	or r24 = r24, r26 ;;
	119	mov psr.l = r24 ;;
[41fa6f2]	120	srlz.i
[293703e]	121	srlz.d ;;
[41fa6f2]	122
[154049e]	123	mov r24 = cr.iip
	124	mov r25 = cr.ipsr
	125	mov r26 = cr.iipa
	126	mov r27 = cr.isr
	127	mov r28 = cr.ifa
[a35b458]	128
[154049e]	129	/* 2. preserve predicate register into bank 0 */
	130	mov r29 = pr ;;
[a35b458]	131
[2262044]	132	/* 3. switch to kernel memory stack */
[83d2d0e]	133	mov r30 = cr.ipsr
[cd373bb]	134	shr.u r31 = r12, VRN_SHIFT ;;
	135
	136	shr.u r30 = r30, PSR_CPL_SHIFT ;;
	137	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
[83d2d0e]	138
	139	/*
[cd373bb]	140	* Set p3 to true if the interrupted context executed in kernel mode.
	141	* Set p4 to false if the interrupted context didn't execute in kernel mode.
[83d2d0e]	142	*/
[cd373bb]	143	cmp.eq p3, p4 = r30, r0 ;;
	144	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
[83d2d0e]	145
	146	/*
[cd373bb]	147	* Set p3 to true if the stack register references kernel address space.
	148	* Set p4 to false if the stack register doesn't reference kernel address space.
[83d2d0e]	149	*/
[901122b]	150	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
[a35b458]	151
[83d2d0e]	152	/*
[cd373bb]	153	* Now, p4 is true iff the stack needs to be switched to kernel stack.
[83d2d0e]	154	*/
	155	mov r30 = r12
[901122b]	156	(p4) mov r12 = R_KSTACK ;;
[a35b458]	157
[293703e]	158	add r12 = -STACK_FRAME_SIZE, r12 ;;
	159	add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_IN6, r12
[e2ec980f]	160
[901122b]	161	/* 4. save registers in bank 0 into memory stack */
	162
	163	/*
	164	* If this is break_instruction handler,
	165	* copy input parameters to stack.
	166	*/
[9928240]	167	cmp.eq p6, p5 = EXC_BREAK_INSTRUCTION, R_VECTOR ;;
[a35b458]	168
[901122b]	169	/*
[1b03ed3]	170	* From now on, if this is break_instruction handler, p6 is true and p5
	171	* is false. Otherwise p6 is false and p5 is true.
[901122b]	172	* Note that p5 is a preserved predicate register and we make use of it.
	173	*/
[5c089c3a]	174
[293703e]	175	(p6) st8 [r31] = r38, -STACK_ITEM_SIZE ;; /* save in6 */
	176	(p6) st8 [r31] = r37, -STACK_ITEM_SIZE ;; /* save in5 */
[1b20da0]	177	(p6) st8 [r31] = r36, -STACK_ITEM_SIZE ;; /* save in4 */
[293703e]	178	(p6) st8 [r31] = r35, -STACK_ITEM_SIZE ;; /* save in3 */
	179	(p6) st8 [r31] = r34, -STACK_ITEM_SIZE ;; /* save in2 */
	180	(p6) st8 [r31] = r33, -STACK_ITEM_SIZE ;; /* save in1 */
	181	(p6) st8 [r31] = r32, -STACK_ITEM_SIZE ;; /* save in0 */
	182	(p5) add r31 = -(7 * STACK_ITEM_SIZE), r31 ;;
[a35b458]	183
[1b20da0]	184	st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save old stack pointer */
[a35b458]	185
[293703e]	186	st8 [r31] = r29, -STACK_ITEM_SIZE ;; /* save predicate registers */
[2262044]	187
[70259a55]	188	mov r29 = cr.iim ;;
	189	st8 [r31] = r29, -STACK_ITEM_SIZE ;; /* save cr.iim */
	190
[293703e]	191	st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save cr.iip */
	192	st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save cr.ipsr */
	193	st8 [r31] = r26, -STACK_ITEM_SIZE ;; /* save cr.iipa */
	194	st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save cr.isr */
	195	st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save cr.ifa */
[2262044]	196
	197	/* 5. RSE switch from interrupted context */
[154049e]	198	mov r24 = ar.rsc
	199	mov r25 = ar.pfs
	200	cover
	201	mov r26 = cr.ifs
[a35b458]	202
[293703e]	203	st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save ar.rsc */
	204	st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save ar.pfs */
	205	st8 [r31] = r26, -STACK_ITEM_SIZE /* save ar.ifs */
[a35b458]	206
[b994a60]	207	and r24 = ~(RSC_PL_MASK), r24 ;;
	208	and r30 = ~(RSC_MODE_MASK), r24 ;;
	209	mov ar.rsc = r30 ;; /* update RSE state */
[a35b458]	210
[154049e]	211	mov r27 = ar.rnat
[e2ec980f]	212	mov r28 = ar.bspstore ;;
[a35b458]	213
[cd373bb]	214	/*
[1b03ed3]	215	* Inspect BSPSTORE to figure out whether it is necessary to switch to
	216	* kernel BSPSTORE.
[cd373bb]	217	*/
[901122b]	218	(p1) shr.u r30 = r28, VRN_SHIFT ;;
	219	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
[a35b458]	220
[cd373bb]	221	/*
	222	* If BSPSTORE needs to be switched, p1 is false and p2 is true.
	223	*/
[901122b]	224	(p1) mov r30 = r28
	225	(p2) mov r30 = R_KSTACK_BSP ;;
	226	(p2) mov ar.bspstore = r30 ;;
[a35b458]	227
[154049e]	228	mov r29 = ar.bsp
[a35b458]	229
[293703e]	230	st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save ar.rnat */
	231	st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save new value written to ar.bspstore */
	232	st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save ar.bspstore */
	233	st8 [r31] = r29, -STACK_ITEM_SIZE /* save ar.bsp */
[a35b458]	234
[b994a60]	235	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
[a35b458]	236
[e2ec980f]	237	/* steps 6 - 15 are done by heavyweight_handler_inner() */
[cd373bb]	238	mov R_RET = b0 /* save b0 belonging to interrupted context */
[bc314be8]	239	br.call.sptk.many b0 = heavyweight_handler_inner
[cd373bb]	240	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
[2262044]	241
[e2ec980f]	242	/* 16. RSE switch to interrupted context */
[1b03ed3]	243	cover /* allocate zero size frame (step 1 (from Intel Docs)) */
[e2ec980f]	244
[293703e]	245	add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_AR_BSP, r12 ;;
[e2ec980f]	246
[293703e]	247	ld8 r30 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bsp */
	248	ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bspstore */
	249	ld8 r28 = [r31], +STACK_ITEM_SIZE ;; /* load ar.bspstore_new */
[e1c68e0c]	250	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
[e2ec980f]	251	shl r27 = r27, 16
	252
	253	mov r24 = ar.rsc ;;
	254	and r30 = ~3, r24 ;;
[1b20da0]	255	or r24 = r30 , r27 ;;
[e2ec980f]	256	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
	257
	258	loadrs /* (step 3) */
	259
[293703e]	260	ld8 r27 = [r31], +STACK_ITEM_SIZE ;; /* load ar.rnat */
	261	ld8 r26 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ifs */
	262	ld8 r25 = [r31], +STACK_ITEM_SIZE ;; /* load ar.pfs */
	263	ld8 r24 = [r31], +STACK_ITEM_SIZE ;; /* load ar.rsc */
[e2ec980f]	264
[e1c68e0c]	265	mov ar.bspstore = r29 ;; /* (step 4) */
	266	mov ar.rnat = r27 /* (step 5) */
[e2ec980f]	267
	268	mov ar.pfs = r25 /* (step 6) */
[1b20da0]	269	mov cr.ifs = r26
[e2ec980f]	270
	271	mov ar.rsc = r24 /* (step 7) */
	272
	273	/* 17. restore interruption state from memory stack */
[1b20da0]	274	ld8 r28 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ifa */
[293703e]	275	ld8 r27 = [r31], +STACK_ITEM_SIZE ;; /* load cr.isr */
	276	ld8 r26 = [r31], +STACK_ITEM_SIZE ;; /* load cr.iipa */
	277	ld8 r25 = [r31], +STACK_ITEM_SIZE ;; /* load cr.ipsr */
	278	ld8 r24 = [r31], +STACK_ITEM_SIZE ;; /* load cr.iip */
[70259a55]	279	ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load cr.iim */
[e2ec980f]	280
[41fa6f2]	281	mov cr.iip = r24;;
[e2ec980f]	282	mov cr.iipa = r26
	283	mov cr.isr = r27
	284	mov cr.ifa = r28
[70259a55]	285	mov cr.iim = r29
[2ba1f39]	286
	287	/* Set up FPU as in exception. */
	288	mov r24 = psr
	289	mov r26 = PSR_DFH_MASK
	290	mov r27 = ~PSR_DFH_MASK ;;
	291	and r25 = r25, r27
	292	and r24 = r24, r26 ;;
[293703e]	293	or r25 = r25, r24 ;;
[41fa6f2]	294	mov cr.ipsr = r25
[e2ec980f]	295
	296	/* 18. restore predicate registers from memory stack */
[293703e]	297	ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load predicate registers */
[e2ec980f]	298	mov pr = r29
[a35b458]	299
[e2ec980f]	300	/* 19. return from interruption */
[1b20da0]	301	ld8 r12 = [r31] /* load stack pointer */
[e2ec980f]	302	rfi ;;
[2262044]	303
[27f67f5]	304	FUNCTION_BEGIN(heavyweight_handler_inner)
[2262044]	305	/*
	306	* From this point, the rest of the interrupted context
	307	* will be preserved in stacked registers and backing store.
	308	*/
[5581c45e]	309	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
[a35b458]	310
[e2ec980f]	311	/* bank 0 is going to be shadowed, copy essential data from there */
[bc314be8]	312	mov loc1 = R_RET /* b0 belonging to interrupted context */
	313	mov loc2 = R_HANDLER
[9928240]	314	mov out0 = R_VECTOR
[a35b458]	315
[e2ec980f]	316	add out1 = STACK_SCRATCH_AREA_SIZE, r12
[2262044]	317
[154049e]	318	/* 6. switch to bank 1 and reenable PSR.ic */
[8a0b3730]	319	ssm PSR_IC_MASK
[154049e]	320	bsw.1 ;;
	321	srlz.d
[a35b458]	322
[154049e]	323	/* 7. preserve branch and application registers */
[e2ec980f]	324	mov loc3 = ar.unat
	325	mov loc4 = ar.lc
	326	mov loc5 = ar.ec
	327	mov loc6 = ar.ccv
	328	mov loc7 = ar.csd
	329	mov loc8 = ar.ssd
[a35b458]	330
[e2ec980f]	331	mov loc9 = b0
	332	mov loc10 = b1
	333	mov loc11 = b2
	334	mov loc12 = b3
	335	mov loc13 = b4
	336	mov loc14 = b5
	337	mov loc15 = b6
	338	mov loc16 = b7
[a35b458]	339
[154049e]	340	/* 8. preserve general and floating-point registers */
[e2ec980f]	341	mov loc17 = r1
	342	mov loc18 = r2
	343	mov loc19 = r3
	344	mov loc20 = r4
	345	mov loc21 = r5
	346	mov loc22 = r6
	347	mov loc23 = r7
[901122b]	348	(p5) mov loc24 = r8 /* only if not in break_instruction handler */
[e2ec980f]	349	mov loc25 = r9
	350	mov loc26 = r10
	351	mov loc27 = r11
[2262044]	352	/* skip r12 (stack pointer) */
[e2ec980f]	353	mov loc28 = r13
	354	mov loc29 = r14
	355	mov loc30 = r15
	356	mov loc31 = r16
	357	mov loc32 = r17
	358	mov loc33 = r18
	359	mov loc34 = r19
	360	mov loc35 = r20
	361	mov loc36 = r21
	362	mov loc37 = r22
	363	mov loc38 = r23
	364	mov loc39 = r24
	365	mov loc40 = r25
	366	mov loc41 = r26
	367	mov loc42 = r27
	368	mov loc43 = r28
	369	mov loc44 = r29
	370	mov loc45 = r30
	371	mov loc46 = r31
[5581c45e]	372
[293703e]	373	add r24 = ISTATE_OFFSET_F8 + STACK_SCRATCH_AREA_SIZE, r12
	374	add r25 = ISTATE_OFFSET_F9 + STACK_SCRATCH_AREA_SIZE, r12
	375	add r26 = ISTATE_OFFSET_F2 + STACK_SCRATCH_AREA_SIZE, r12
	376	add r27 = ISTATE_OFFSET_F3 + STACK_SCRATCH_AREA_SIZE, r12
	377	add r28 = ISTATE_OFFSET_F4 + STACK_SCRATCH_AREA_SIZE, r12
	378	add r29 = ISTATE_OFFSET_F5 + STACK_SCRATCH_AREA_SIZE, r12
	379	add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12
	380	add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;;
[a35b458]	381
[293703e]	382	stf.spill [r26] = f2, 8 * FLOAT_ITEM_SIZE
	383	stf.spill [r27] = f3, 8 * FLOAT_ITEM_SIZE
	384	stf.spill [r28] = f4, 8 * FLOAT_ITEM_SIZE
	385	stf.spill [r29] = f5, 8 * FLOAT_ITEM_SIZE
	386	stf.spill [r30] = f6, 8 * FLOAT_ITEM_SIZE
	387	stf.spill [r31] = f7, 8 * FLOAT_ITEM_SIZE ;;
	388
	389	stf.spill [r24] = f8, 8 * FLOAT_ITEM_SIZE
	390	stf.spill [r25] = f9, 8 * FLOAT_ITEM_SIZE
	391	stf.spill [r26] = f10, 8 * FLOAT_ITEM_SIZE
	392	stf.spill [r27] = f11, 8 * FLOAT_ITEM_SIZE
	393	stf.spill [r28] = f12, 8 * FLOAT_ITEM_SIZE
	394	stf.spill [r29] = f13, 8 * FLOAT_ITEM_SIZE
	395	stf.spill [r30] = f14, 8 * FLOAT_ITEM_SIZE
	396	stf.spill [r31] = f15, 8 * FLOAT_ITEM_SIZE ;;
	397
[1b20da0]	398	stf.spill [r24] = f16, 8 * FLOAT_ITEM_SIZE
[293703e]	399	stf.spill [r25] = f17, 8 * FLOAT_ITEM_SIZE
	400	stf.spill [r26] = f18, 8 * FLOAT_ITEM_SIZE
	401	stf.spill [r27] = f19, 8 * FLOAT_ITEM_SIZE
	402	stf.spill [r28] = f20, 8 * FLOAT_ITEM_SIZE
	403	stf.spill [r29] = f21, 8 * FLOAT_ITEM_SIZE
	404	stf.spill [r30] = f22, 8 * FLOAT_ITEM_SIZE
	405	stf.spill [r31] = f23, 8 * FLOAT_ITEM_SIZE ;;
	406
	407	stf.spill [r24] = f24
	408	stf.spill [r25] = f25
	409	stf.spill [r26] = f26
	410	stf.spill [r27] = f27
	411	stf.spill [r28] = f28
	412	stf.spill [r29] = f29
	413	stf.spill [r30] = f30
	414	stf.spill [r31] = f31 ;;
[2ba1f39]	415
	416	mov loc47 = ar.fpsr /* preserve floating point status register */
[a35b458]	417
[154049e]	418	/* 9. skipped (will not enable interrupts) */
[8a0b3730]	419	/*
	420	* ssm PSR_I_MASK
	421	* ;;
	422	* srlz.d
	423	*/
[154049e]	424
[2262044]	425	/* 10. call handler */
[18ba2e4f]	426	movl r1 = __gp
[a35b458]	427
[e2ec980f]	428	mov b1 = loc2
[2262044]	429	br.call.sptk.many b0 = b1
	430
	431	/* 11. return from handler */
	432	0:
[a35b458]	433
[2262044]	434	/* 12. skipped (will not disable interrupts) */
[8a0b3730]	435	/*
	436	* rsm PSR_I_MASK
	437	* ;;
	438	* srlz.d
	439	*/
[2262044]	440
[154049e]	441	/* 13. restore general and floating-point registers */
[293703e]	442	add r24 = ISTATE_OFFSET_F8 + STACK_SCRATCH_AREA_SIZE, r12
	443	add r25 = ISTATE_OFFSET_F9 + STACK_SCRATCH_AREA_SIZE, r12
	444	add r26 = ISTATE_OFFSET_F2 + STACK_SCRATCH_AREA_SIZE, r12
	445	add r27 = ISTATE_OFFSET_F3 + STACK_SCRATCH_AREA_SIZE, r12
	446	add r28 = ISTATE_OFFSET_F4 + STACK_SCRATCH_AREA_SIZE, r12
	447	add r29 = ISTATE_OFFSET_F5 + STACK_SCRATCH_AREA_SIZE, r12
	448	add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12
	449	add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;;
	450
	451	ldf.fill f2 = [r26], 8 * FLOAT_ITEM_SIZE
	452	ldf.fill f3 = [r27], 8 * FLOAT_ITEM_SIZE
	453	ldf.fill f4 = [r28], 8 * FLOAT_ITEM_SIZE
	454	ldf.fill f5 = [r29], 8 * FLOAT_ITEM_SIZE
	455	ldf.fill f6 = [r30], 8 * FLOAT_ITEM_SIZE
	456	ldf.fill f7 = [r31], 8 * FLOAT_ITEM_SIZE ;;
	457
	458	ldf.fill f8 = [r24], 8 * FLOAT_ITEM_SIZE
	459	ldf.fill f9 = [r25], 8 * FLOAT_ITEM_SIZE
	460	ldf.fill f10 = [r26],8 * FLOAT_ITEM_SIZE
	461	ldf.fill f11 = [r27], 8 * FLOAT_ITEM_SIZE
	462	ldf.fill f12 = [r28], 8 * FLOAT_ITEM_SIZE
	463	ldf.fill f13 = [r29], 8 * FLOAT_ITEM_SIZE
	464	ldf.fill f14 = [r30], 8 * FLOAT_ITEM_SIZE
	465	ldf.fill f15 = [r31], 8 * FLOAT_ITEM_SIZE ;;
	466
	467	ldf.fill f16 = [r24], 8 * FLOAT_ITEM_SIZE
	468	ldf.fill f17 = [r25], 8 * FLOAT_ITEM_SIZE
	469	ldf.fill f18 = [r26], 8 * FLOAT_ITEM_SIZE
	470	ldf.fill f19 = [r27], 8 * FLOAT_ITEM_SIZE
	471	ldf.fill f20 = [r28], 8 * FLOAT_ITEM_SIZE
	472	ldf.fill f21 = [r29], 8 * FLOAT_ITEM_SIZE
	473	ldf.fill f22 = [r30], 8 * FLOAT_ITEM_SIZE
	474	ldf.fill f23 = [r31], 8 * FLOAT_ITEM_SIZE ;;
	475
	476	ldf.fill f24 = [r24]
	477	ldf.fill f25 = [r25]
	478	ldf.fill f26 = [r26]
	479	ldf.fill f27 = [r27]
	480	ldf.fill f28 = [r28]
	481	ldf.fill f29 = [r29]
	482	ldf.fill f30 = [r30]
	483	ldf.fill f31 = [r31] ;;
[a35b458]	484
[e2ec980f]	485	mov r1 = loc17
	486	mov r2 = loc18
	487	mov r3 = loc19
	488	mov r4 = loc20
	489	mov r5 = loc21
	490	mov r6 = loc22
	491	mov r7 = loc23
[901122b]	492	(p5) mov r8 = loc24 /* only if not in break_instruction handler */
[e2ec980f]	493	mov r9 = loc25
	494	mov r10 = loc26
	495	mov r11 = loc27
[2262044]	496	/* skip r12 (stack pointer) */
[e2ec980f]	497	mov r13 = loc28
	498	mov r14 = loc29
	499	mov r15 = loc30
	500	mov r16 = loc31
	501	mov r17 = loc32
	502	mov r18 = loc33
	503	mov r19 = loc34
	504	mov r20 = loc35
	505	mov r21 = loc36
	506	mov r22 = loc37
	507	mov r23 = loc38
	508	mov r24 = loc39
	509	mov r25 = loc40
[1b20da0]	510	mov r26 = loc41
[e2ec980f]	511	mov r27 = loc42
	512	mov r28 = loc43
	513	mov r29 = loc44
	514	mov r30 = loc45
	515	mov r31 = loc46
[2ba1f39]	516
	517	mov ar.fpsr = loc47 /* restore floating point status register */
[a35b458]	518
[154049e]	519	/* 14. restore branch and application registers */
[e2ec980f]	520	mov ar.unat = loc3
	521	mov ar.lc = loc4
	522	mov ar.ec = loc5
	523	mov ar.ccv = loc6
	524	mov ar.csd = loc7
	525	mov ar.ssd = loc8
[a35b458]	526
[e2ec980f]	527	mov b0 = loc9
	528	mov b1 = loc10
	529	mov b2 = loc11
	530	mov b3 = loc12
	531	mov b4 = loc13
	532	mov b5 = loc14
	533	mov b6 = loc15
	534	mov b7 = loc16
[a35b458]	535
[154049e]	536	/* 15. disable PSR.ic and switch to bank 0 */
[8a0b3730]	537	rsm PSR_IC_MASK
[154049e]	538	bsw.0 ;;
	539	srlz.d
[2262044]	540
[bc314be8]	541	mov R_RET = loc1
[2262044]	542	mov ar.pfs = loc0
[e2ec980f]	543	br.ret.sptk.many b0
[27f67f5]	544	FUNCTION_END(heavyweight_handler_inner)
[d2bb9f8a]	545
	546	.align 32768
[27f67f5]	547	SYMBOL(ivt)
[9928240]	548	HEAVYWEIGHT_HANDLER 0x00
	549	HEAVYWEIGHT_HANDLER 0x04
	550	HEAVYWEIGHT_HANDLER 0x08
	551	HEAVYWEIGHT_HANDLER 0x0c
	552	HEAVYWEIGHT_HANDLER 0x10
	553	HEAVYWEIGHT_HANDLER 0x14
	554	HEAVYWEIGHT_HANDLER 0x18
	555	HEAVYWEIGHT_HANDLER 0x1c
	556	HEAVYWEIGHT_HANDLER 0x20
	557	HEAVYWEIGHT_HANDLER 0x24
	558	HEAVYWEIGHT_HANDLER 0x28
	559	HEAVYWEIGHT_HANDLER 0x2c break_instruction
	560	HEAVYWEIGHT_HANDLER 0x30
	561	HEAVYWEIGHT_HANDLER 0x34
	562	HEAVYWEIGHT_HANDLER 0x38
	563	HEAVYWEIGHT_HANDLER 0x3c
	564	HEAVYWEIGHT_HANDLER 0x40
	565	HEAVYWEIGHT_HANDLER 0x44
	566	HEAVYWEIGHT_HANDLER 0x48
	567	HEAVYWEIGHT_HANDLER 0x4c
	568
	569	HEAVYWEIGHT_HANDLER 0x50
	570	HEAVYWEIGHT_HANDLER 0x51
	571	HEAVYWEIGHT_HANDLER 0x52
	572	HEAVYWEIGHT_HANDLER 0x53
	573	HEAVYWEIGHT_HANDLER 0x54
	574	HEAVYWEIGHT_HANDLER 0x55
	575	HEAVYWEIGHT_HANDLER 0x56
	576	SPECULATION_VECTOR_HANDLER 0x57
	577	HEAVYWEIGHT_HANDLER 0x58
	578	HEAVYWEIGHT_HANDLER 0x59
	579	HEAVYWEIGHT_HANDLER 0x5a
	580	HEAVYWEIGHT_HANDLER 0x5b
	581	HEAVYWEIGHT_HANDLER 0x5c
[1b20da0]	582	HEAVYWEIGHT_HANDLER 0x5d
[9928240]	583	HEAVYWEIGHT_HANDLER 0x5e
	584	HEAVYWEIGHT_HANDLER 0x5f
[a35b458]	585
[9928240]	586	HEAVYWEIGHT_HANDLER 0x60
	587	HEAVYWEIGHT_HANDLER 0x61
	588	HEAVYWEIGHT_HANDLER 0x62
	589	HEAVYWEIGHT_HANDLER 0x63
	590	HEAVYWEIGHT_HANDLER 0x64
	591	HEAVYWEIGHT_HANDLER 0x65
	592	HEAVYWEIGHT_HANDLER 0x66
	593	HEAVYWEIGHT_HANDLER 0x67
	594	HEAVYWEIGHT_HANDLER 0x68
	595	HEAVYWEIGHT_HANDLER 0x69
	596	HEAVYWEIGHT_HANDLER 0x6a
	597	HEAVYWEIGHT_HANDLER 0x6b
	598	HEAVYWEIGHT_HANDLER 0x6c
	599	HEAVYWEIGHT_HANDLER 0x6d
	600	HEAVYWEIGHT_HANDLER 0x6e
	601	HEAVYWEIGHT_HANDLER 0x6f
	602
	603	HEAVYWEIGHT_HANDLER 0x70
	604	HEAVYWEIGHT_HANDLER 0x71
	605	HEAVYWEIGHT_HANDLER 0x72
	606	HEAVYWEIGHT_HANDLER 0x73
	607	HEAVYWEIGHT_HANDLER 0x74
	608	HEAVYWEIGHT_HANDLER 0x75
	609	HEAVYWEIGHT_HANDLER 0x76
	610	HEAVYWEIGHT_HANDLER 0x77
	611	HEAVYWEIGHT_HANDLER 0x78
	612	HEAVYWEIGHT_HANDLER 0x79
	613	HEAVYWEIGHT_HANDLER 0x7a
	614	HEAVYWEIGHT_HANDLER 0x7b
	615	HEAVYWEIGHT_HANDLER 0x7c
	616	HEAVYWEIGHT_HANDLER 0x7d
	617	HEAVYWEIGHT_HANDLER 0x7e
	618	HEAVYWEIGHT_HANDLER 0x7f

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