source: mainline/kernel/arch/ia64/src/interrupt.c@ 1b03ed3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 1b03ed3 was 1b03ed3, checked in by Jakub Jermar <jakub@…>, 18 years ago

Support for six syscall arguments on ia64.

—iSupis line, and those below, will be ignored—

M kernel/arch/ia64/include/interrupt.h
M kernel/arch/ia64/src/ivt.S
M kernel/arch/ia64/src/interrupt.c
M uspace/lib/libc/arch/ia64/src/syscall.S

  • Property mode set to 100644
File size: 6.8 KB
RevLine 
[dbd1059]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
3 * Copyright (c) 2005 Jakub Vana
[dbd1059]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
[b45c443]28 */
29
[b6529ae]30/** @addtogroup ia64interrupt
[b45c443]31 * @{
32 */
33/** @file
[dbd1059]34 */
35
36#include <arch/interrupt.h>
[de57e060]37#include <interrupt.h>
38#include <ddi/irq.h>
[dbd1059]39#include <panic.h>
[05d9dd89]40#include <print.h>
[de57e060]41#include <symtab.h>
42#include <debug.h>
[72f5866d]43#include <console/console.h>
[dbd1059]44#include <arch/types.h>
45#include <arch/asm.h>
46#include <arch/barrier.h>
[0259524]47#include <arch/register.h>
[05d9dd89]48#include <arch.h>
[901122b]49#include <syscall/syscall.h>
50#include <print.h>
[9e1c942]51#include <proc/scheduler.h>
[953b0f33]52#include <ipc/sysipc.h>
[d0c5901]53#include <ipc/irq.h>
54#include <ipc/ipc.h>
[de57e060]55#include <synch/spinlock.h>
[dbd1059]56
[e2ec980f]57#define VECTORS_64_BUNDLE 20
58#define VECTORS_16_BUNDLE 48
59#define VECTORS_16_BUNDLE_START 0x5000
60#define VECTOR_MAX 0x7f00
61
62#define BUNDLE_SIZE 16
63
64char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
65 "VHPT Translation vector",
66 "Instruction TLB vector",
67 "Data TLB vector",
68 "Alternate Instruction TLB vector",
69 "Alternate Data TLB vector",
70 "Data Nested TLB vector",
71 "Instruction Key Miss vector",
72 "Data Key Miss vector",
73 "Dirty-Bit vector",
74 "Instruction Access-Bit vector",
75 "Data Access-Bit vector"
76 "Break Instruction vector",
77 "External Interrupt vector"
78 "Reserved",
79 "Reserved",
80 "Reserved",
81 "Reserved",
82 "Reserved",
83 "Reserved",
84 "Reserved"
85};
86
87char *vector_names_16_bundle[VECTORS_16_BUNDLE] = {
88 "Page Not Present vector",
89 "Key Permission vector",
90 "Instruction Access rights vector",
91 "Data Access Rights vector",
92 "General Exception vector",
93 "Disabled FP-Register vector",
94 "NaT Consumption vector",
95 "Speculation vector",
96 "Reserved",
97 "Debug vector",
98 "Unaligned Reference vector",
99 "Unsupported Data Reference vector",
100 "Floating-point Fault vector",
101 "Floating-point Trap vector",
102 "Lower-Privilege Transfer Trap vector",
103 "Taken Branch Trap vector",
[66eb2c8]104 "Single Step Trap vector",
[e2ec980f]105 "Reserved",
106 "Reserved",
107 "Reserved",
108 "Reserved",
109 "Reserved",
110 "Reserved",
111 "Reserved",
112 "Reserved",
113 "IA-32 Exception vector",
114 "IA-32 Intercept vector",
115 "IA-32 Interrupt vector",
116 "Reserved",
117 "Reserved",
118 "Reserved"
119};
120
[7f1c620]121static char *vector_to_string(uint16_t vector);
[25d7709]122static void dump_interrupted_context(istate_t *istate);
[e2ec980f]123
[7f1c620]124char *vector_to_string(uint16_t vector)
[e2ec980f]125{
126 ASSERT(vector <= VECTOR_MAX);
127
128 if (vector >= VECTORS_16_BUNDLE_START)
[1b03ed3]129 return vector_names_16_bundle[(vector -
130 VECTORS_16_BUNDLE_START) / (16 * BUNDLE_SIZE)];
[e2ec980f]131 else
[1b03ed3]132 return vector_names_64_bundle[vector / (64 * BUNDLE_SIZE)];
[e2ec980f]133}
134
[25d7709]135void dump_interrupted_context(istate_t *istate)
[e2ec980f]136{
137 char *ifa, *iipa, *iip;
138
[25d7709]139 ifa = get_symtab_entry(istate->cr_ifa);
140 iipa = get_symtab_entry(istate->cr_iipa);
141 iip = get_symtab_entry(istate->cr_iip);
[e2ec980f]142
143 putchar('\n');
[2ccd275]144 printf("Interrupted context dump:\n");
[1b03ed3]145 printf("ar.bsp=%p\tar.bspstore=%p\n", istate->ar_bsp,
146 istate->ar_bspstore);
147 printf("ar.rnat=%#018llx\tar.rsc=%#018llx\n", istate->ar_rnat,
148 istate->ar_rsc);
149 printf("ar.ifs=%#018llx\tar.pfs=%#018llx\n", istate->ar_ifs,
150 istate->ar_pfs);
151 printf("cr.isr=%#018llx\tcr.ipsr=%#018llx\t\n", istate->cr_isr.value,
152 istate->cr_ipsr);
[e2ec980f]153
[1b03ed3]154 printf("cr.iip=%#018llx, #%d\t(%s)\n", istate->cr_iip,
155 istate->cr_isr.ei, iip);
[d0c5901]156 printf("cr.iipa=%#018llx\t(%s)\n", istate->cr_iipa, iipa);
157 printf("cr.ifa=%#018llx\t(%s)\n", istate->cr_ifa, ifa);
[e2ec980f]158}
159
[7f1c620]160void general_exception(uint64_t vector, istate_t *istate)
[e2ec980f]161{
[2ccd275]162 char *desc = "";
163
[25d7709]164 switch (istate->cr_isr.ge_code) {
[6eabb6e6]165 case GE_ILLEGALOP:
[2ccd275]166 desc = "Illegal Operation fault";
167 break;
[6eabb6e6]168 case GE_PRIVOP:
[2ccd275]169 desc = "Privileged Operation fault";
170 break;
[6eabb6e6]171 case GE_PRIVREG:
[2ccd275]172 desc = "Privileged Register fault";
173 break;
[6eabb6e6]174 case GE_RESREGFLD:
[2ccd275]175 desc = "Reserved Register/Field fault";
176 break;
[6eabb6e6]177 case GE_DISBLDISTRAN:
[2ccd275]178 desc = "Disabled Instruction Set Transition fault";
179 break;
[6eabb6e6]180 case GE_ILLEGALDEP:
[2ccd275]181 desc = "Illegal Dependency fault";
182 break;
[6eabb6e6]183 default:
184 desc = "unknown";
[2ccd275]185 break;
186 }
187
[874621f]188 fault_if_from_uspace(istate, "General Exception (%s)", desc);
189
190 dump_interrupted_context(istate);
[2ccd275]191 panic("General Exception (%s)\n", desc);
[e2ec980f]192}
193
[7f1c620]194void disabled_fp_register(uint64_t vector, istate_t *istate)
[9e1c942]195{
[41fa6f2]196#ifdef CONFIG_FPU_LAZY
[9e1c942]197 scheduler_fpu_lazy_request();
[41fa6f2]198#else
[1b03ed3]199 fault_if_from_uspace(istate, "Interruption: %#hx (%s)",
200 (uint16_t) vector, vector_to_string(vector));
[41fa6f2]201 dump_interrupted_context(istate);
[1b03ed3]202 panic("Interruption: %#hx (%s)\n", (uint16_t) vector,
203 vector_to_string(vector));
[9e1c942]204#endif
205}
206
[7f1c620]207void nop_handler(uint64_t vector, istate_t *istate)
[9e1c942]208{
209}
210
[901122b]211/** Handle syscall. */
[7f1c620]212int break_instruction(uint64_t vector, istate_t *istate)
[e2ec980f]213{
[901122b]214 /*
215 * Move to next instruction after BREAK.
216 */
[25d7709]217 if (istate->cr_ipsr.ri == 2) {
218 istate->cr_ipsr.ri = 0;
219 istate->cr_iip += 16;
[901122b]220 } else {
[25d7709]221 istate->cr_ipsr.ri++;
[901122b]222 }
223
[1b03ed3]224 return syscall_handler(istate->in0, istate->in1, istate->in2,
225 istate->in3, istate->in4, istate->in5, istate->in6);
[e2ec980f]226}
227
[7f1c620]228void universal_handler(uint64_t vector, istate_t *istate)
[e2ec980f]229{
[1b03ed3]230 fault_if_from_uspace(istate, "Interruption: %#hx (%s)\n",
231 (uint16_t) vector, vector_to_string(vector));
[25d7709]232 dump_interrupted_context(istate);
[1b03ed3]233 panic("Interruption: %#hx (%s)\n", (uint16_t) vector,
234 vector_to_string(vector));
[e2ec980f]235}
236
[7f1c620]237void external_interrupt(uint64_t vector, istate_t *istate)
[dbd1059]238{
[de57e060]239 irq_t *irq;
[05d9dd89]240 cr_ivr_t ivr;
[dbd1059]241
[05d9dd89]242 ivr.value = ivr_read();
[dbd1059]243 srlz_d();
[83817ea]244
[de57e060]245 irq = irq_dispatch_and_lock(ivr.vector);
246 if (irq) {
247 irq->handler(irq, irq->arg);
248 spinlock_unlock(&irq->lock);
249 } else {
250 switch (ivr.vector) {
251 case INTERRUPT_SPURIOUS:
252#ifdef CONFIG_DEBUG
253 printf("cpu%d: spurious interrupt\n", CPU->id);
254#endif
255 break;
[953b0f33]256
[de57e060]257 default:
[1b03ed3]258 panic("\nUnhandled External Interrupt Vector %d\n",
259 ivr.vector);
[de57e060]260 break;
261 }
[d0c5901]262 }
263}
264
[3222efd]265/** @}
[b45c443]266 */
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