source: mainline/kernel/arch/ia64/src/ia64.c@ 494a54a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 494a54a was 26678e5, checked in by Jakub Jermar <jakub@…>, 19 years ago

Make SMP related parts of main.c more generic.
Move initialization of local APIC to architecture specific code.
Add arch_post_cpu_init() to support the above.

  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <arch/ski/ski.h>
37#include <arch/drivers/it.h>
38#include <arch/interrupt.h>
39#include <arch/barrier.h>
40#include <arch/asm.h>
41#include <arch/register.h>
42#include <arch/types.h>
43#include <arch/context.h>
44#include <arch/stack.h>
45#include <arch/mm/page.h>
46#include <mm/as.h>
47#include <config.h>
48#include <userspace.h>
49#include <console/console.h>
50#include <proc/uarg.h>
51#include <syscall/syscall.h>
52
53static int kbd_release=0;
54
55void arch_pre_main(void)
56{
57 /* Setup usermode init tasks. */
58 init.cnt = 8;
59 init.tasks[0].addr = INIT0_ADDRESS;
60 init.tasks[0].size = INIT0_SIZE;
61 init.tasks[1].addr = INIT0_ADDRESS + 0x400000;
62 init.tasks[1].size = INIT0_SIZE;
63 init.tasks[2].addr = INIT0_ADDRESS + 0x800000;
64 init.tasks[2].size = INIT0_SIZE;
65 init.tasks[3].addr = INIT0_ADDRESS + 0xc00000;
66 init.tasks[3].size = INIT0_SIZE;
67 init.tasks[4].addr = INIT0_ADDRESS + 0x1000000;
68 init.tasks[4].size = INIT0_SIZE;
69 init.tasks[5].addr = INIT0_ADDRESS + 0x1400000;
70 init.tasks[5].size = INIT0_SIZE;
71 init.tasks[6].addr = INIT0_ADDRESS + 0x1800000;
72 init.tasks[6].size = INIT0_SIZE;
73 init.tasks[7].addr = INIT0_ADDRESS + 0x1c00000;
74 init.tasks[7].size = INIT0_SIZE;
75}
76
77void arch_pre_mm_init(void)
78{
79 /* Set Interruption Vector Address (i.e. location of interruption vector table). */
80 iva_write((uintptr_t) &ivt);
81 srlz_d();
82
83 ski_init_console();
84 it_init();
85}
86
87void arch_post_mm_init(void)
88{
89 ski_set_console_sysinfo();
90}
91
92void arch_post_cpu_init(void)
93{
94}
95
96void arch_pre_smp_init(void)
97{
98}
99
100void arch_post_smp_init(void)
101{
102}
103
104/** Enter userspace and never return. */
105void userspace(uspace_arg_t *kernel_uarg)
106{
107 psr_t psr;
108 rsc_t rsc;
109
110 psr.value = psr_read();
111 psr.cpl = PL_USER;
112 psr.i = true; /* start with interrupts enabled */
113 psr.ic = true;
114 psr.ri = 0; /* start with instruction #0 */
115 psr.bn = 1; /* start in bank 0 */
116
117 __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
118 rsc.loadrs = 0;
119 rsc.be = false;
120 rsc.pl = PL_USER;
121 rsc.mode = 3; /* eager mode */
122
123 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
124 ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
125 ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE,
126 (uintptr_t) kernel_uarg->uspace_uarg,
127 psr.value, rsc.value);
128
129 while (1) {
130 ;
131 }
132}
133
134/** Set thread-local-storage pointer.
135 *
136 * We use r13 (a.k.a. tp) for this purpose.
137 */
138unative_t sys_tls_set(unative_t addr)
139{
140 return 0;
141}
142
143/** Acquire console back for kernel
144 *
145 */
146void arch_grab_console(void)
147{
148 kbd_release=kbd_uspace;
149 kbd_uspace=0;
150}
151/** Return console to userspace
152 *
153 */
154void arch_release_console(void)
155{
156 kbd_uspace=kbd_release;
157}
158
159/** @}
160 */
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