source: mainline/kernel/arch/ia64/src/ia64.c@ 38b0ae2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 38b0ae2 was 38b0ae2, checked in by GitHub <noreply@…>, 7 years ago

Generalize ns16550 driver to work with more chips. (#20)

Some UART controllers are compatible with 16550A, but have more spacing
between registers. In particular, ARMADA 385, which is the basis of
Turris Omnia router, has a compatible UART with 32b registers instead of 8b
(with the top three bytes unused).

Note: The device tree file hints that some UARTs may need register reads/writes
that are wider than 8 bits, and this commit does not address that possibility.
  • Property mode set to 100644
File size: 7.3 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <arch/arch.h>
37#include <typedefs.h>
38#include <errno.h>
39#include <interrupt.h>
40#include <arch/interrupt.h>
41#include <macros.h>
42#include <str.h>
43#include <userspace.h>
44#include <console/console.h>
45#include <syscall/syscall.h>
46#include <sysinfo/sysinfo.h>
47#include <arch/drivers/it.h>
48#include <arch/drivers/kbd.h>
49#include <arch/legacyio.h>
50#include <genarch/drivers/ega/ega.h>
51#include <genarch/drivers/i8042/i8042.h>
52#include <genarch/drivers/ns16550/ns16550.h>
53#include <genarch/drivers/legacy/ia32/io.h>
54#include <genarch/kbrd/kbrd.h>
55#include <genarch/srln/srln.h>
56#include <mm/page.h>
57#include <mm/km.h>
58
59#ifdef MACHINE_ski
60#include <arch/drivers/ski.h>
61#endif
62
63static void ia64_pre_mm_init(void);
64static void ia64_post_mm_init(void);
65static void ia64_post_smp_init(void);
66
67arch_ops_t ia64_ops = {
68 .pre_mm_init = ia64_pre_mm_init,
69 .post_mm_init = ia64_post_mm_init,
70 .post_smp_init = ia64_post_smp_init,
71};
72
73arch_ops_t *arch_ops = &ia64_ops;
74
75/* NS16550 as a COM 1 */
76#define NS16550_IRQ (4 + LEGACY_INTERRUPT_BASE)
77
78bootinfo_t *bootinfo;
79
80static uint64_t iosapic_base = 0xfec00000;
81uintptr_t legacyio_virt_base = 0;
82
83/** Performs ia64-specific initialization before main_bsp() is called. */
84void ia64_pre_main(void)
85{
86 init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS,
87 CONFIG_INIT_TASKS);
88 size_t i;
89
90 for (i = 0; i < init.cnt; i++) {
91 init.tasks[i].paddr =
92 (uintptr_t) bootinfo->taskmap.tasks[i].addr;
93 init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
94 str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
95 bootinfo->taskmap.tasks[i].name);
96 }
97}
98
99void ia64_pre_mm_init(void)
100{
101 if (config.cpu_active == 1)
102 exception_init();
103}
104
105static void iosapic_init(void)
106{
107 uintptr_t IOSAPIC = km_map(iosapic_base, PAGE_SIZE,
108 PAGE_WRITE | PAGE_NOT_CACHEABLE);
109 int i;
110
111 int myid, myeid;
112
113 myid = ia64_get_cpu_id();
114 myeid = ia64_get_cpu_eid();
115
116 for (i = 0; i < 16; i++) {
117 if (i == 2)
118 continue; /* Disable Cascade interrupt */
119 ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i;
120 srlz_d();
121 ((uint32_t *)(IOSAPIC + 0x10))[0] = LEGACY_INTERRUPT_BASE + i;
122 srlz_d();
123 ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i + 1;
124 srlz_d();
125 ((uint32_t *)(IOSAPIC + 0x10))[0] = myid << (56 - 32) |
126 myeid << (48 - 32);
127 srlz_d();
128 }
129
130}
131
132void ia64_post_mm_init(void)
133{
134 if (config.cpu_active == 1) {
135 /* Map the page with legacy I/O. */
136 legacyio_virt_base = km_map(LEGACYIO_PHYS_BASE, LEGACYIO_SIZE,
137 PAGE_WRITE | PAGE_NOT_CACHEABLE);
138
139 iosapic_init();
140 irq_init(INR_COUNT, INR_COUNT);
141 }
142 it_init();
143}
144
145void ia64_post_smp_init(void)
146{
147 static const char *platform;
148
149 /* Set platform name. */
150#ifdef MACHINE_ski
151 platform = "ski";
152#endif
153#ifdef MACHINE_i460GX
154 platform = "pc";
155#endif
156 sysinfo_set_item_data("platform", NULL, (void *) platform,
157 str_size(platform));
158
159#ifdef MACHINE_ski
160 ski_instance_t *ski_instance = skiin_init();
161 if (ski_instance) {
162 srln_instance_t *srln_instance = srln_init();
163 if (srln_instance) {
164 indev_t *sink = stdin_wire();
165 indev_t *srln = srln_wire(srln_instance, sink);
166 skiin_wire(ski_instance, srln);
167 }
168 }
169
170 outdev_t *skidev = skiout_init();
171 if (skidev)
172 stdout_wire(skidev);
173#endif
174
175#ifdef CONFIG_EGA
176 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
177 if (egadev)
178 stdout_wire(egadev);
179#endif
180
181#ifdef CONFIG_NS16550
182 ns16550_instance_t *ns16550_instance
183 = ns16550_init(NS16550_BASE, 0, NS16550_IRQ, NULL, NULL,
184 NULL);
185 if (ns16550_instance) {
186 srln_instance_t *srln_instance = srln_init();
187 if (srln_instance) {
188 indev_t *sink = stdin_wire();
189 indev_t *srln = srln_wire(srln_instance, sink);
190 ns16550_wire(ns16550_instance, srln);
191 }
192 }
193
194 sysinfo_set_item_val("kbd", NULL, true);
195 sysinfo_set_item_val("kbd.inr", NULL, NS16550_IRQ);
196 sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
197 sysinfo_set_item_val("kbd.address.physical", NULL,
198 (uintptr_t) NS16550_BASE);
199#endif
200
201#ifdef CONFIG_I8042
202 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE,
203 IRQ_KBD);
204 if (i8042_instance) {
205 kbrd_instance_t *kbrd_instance = kbrd_init();
206 if (kbrd_instance) {
207 indev_t *sink = stdin_wire();
208 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
209 i8042_wire(i8042_instance, kbrd);
210 }
211 }
212#endif
213
214 sysinfo_set_item_val("ia64_iospace", NULL, true);
215 sysinfo_set_item_val("ia64_iospace.address", NULL, true);
216 sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, LEGACYIO_USER_BASE);
217}
218
219
220/** Enter userspace and never return. */
221void userspace(uspace_arg_t *kernel_uarg)
222{
223 psr_t psr;
224 rsc_t rsc;
225
226 psr.value = psr_read();
227 psr.cpl = PL_USER;
228 psr.i = true; /* start with interrupts enabled */
229 psr.ic = true;
230 psr.ri = 0; /* start with instruction #0 */
231 psr.bn = 1; /* start in bank 0 */
232
233 asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
234 rsc.loadrs = 0;
235 rsc.be = false;
236 rsc.pl = PL_USER;
237 rsc.mode = 3; /* eager mode */
238
239 /*
240 * Switch to userspace.
241 *
242 * When calculating stack addresses, mind the stack split between the
243 * memory stack and the RSE stack. Each occuppies
244 * uspace_stack_size / 2 bytes.
245 */
246 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
247 ((uintptr_t) kernel_uarg->uspace_stack) +
248 kernel_uarg->uspace_stack_size / 2 -
249 ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
250 ((uintptr_t) kernel_uarg->uspace_stack) +
251 kernel_uarg->uspace_stack_size / 2,
252 (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
253
254 while (1);
255}
256
257void arch_reboot(void)
258{
259 pio_write_8((ioport8_t *)0x64, 0xfe);
260 while (1);
261}
262
263/** Construct function pointer
264 *
265 * @param fptr function pointer structure
266 * @param addr function address
267 * @param caller calling function address
268 *
269 * @return address of the function pointer
270 *
271 */
272void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
273{
274 fptr->fnc = (sysarg_t) addr;
275 fptr->gp = ((sysarg_t *) caller)[1];
276
277 return (void *) fptr;
278}
279
280void irq_initialize_arch(irq_t *irq)
281{
282 (void) irq;
283}
284
285/** @}
286 */
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