source: mainline/kernel/arch/ia64/src/ia64.c@ b44939b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b44939b was 06e1e95, checked in by Jakub Jermar <jakub@…>, 19 years ago

C99 compliant header guards (hopefully) everywhere in the kernel.
Formatting and indentation changes.
Small improvements in sparc64.

  • Property mode set to 100644
File size: 4.1 KB
RevLine 
[2a0047fc]1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[244f284]35#include <arch.h>
36#include <arch/ski/ski.h>
[154049e]37#include <arch/drivers/it.h>
[e2ec980f]38#include <arch/interrupt.h>
39#include <arch/barrier.h>
[b994a60]40#include <arch/asm.h>
41#include <arch/register.h>
[e2ec980f]42#include <arch/types.h>
[b994a60]43#include <arch/context.h>
[5c089c3a]44#include <arch/stack.h>
[b994a60]45#include <arch/mm/page.h>
46#include <mm/as.h>
47#include <config.h>
48#include <userspace.h>
[a8c48241]49#include <console/console.h>
[0f250f9]50#include <proc/uarg.h>
[e1be3b6]51#include <syscall/syscall.h>
[244f284]52
[586262f]53static int kbd_release=0;
54
[6ecc8bce]55void arch_pre_main(void)
56{
57 /* Setup usermode init tasks. */
[3247f0a]58 init.cnt = 8;
[6ecc8bce]59 init.tasks[0].addr = INIT0_ADDRESS;
60 init.tasks[0].size = INIT0_SIZE;
[f8d069e8]61 init.tasks[1].addr = INIT0_ADDRESS + 0x400000;
62 init.tasks[1].size = INIT0_SIZE;
63 init.tasks[2].addr = INIT0_ADDRESS + 0x800000;
64 init.tasks[2].size = INIT0_SIZE;
65 init.tasks[3].addr = INIT0_ADDRESS + 0xc00000;
66 init.tasks[3].size = INIT0_SIZE;
67 init.tasks[4].addr = INIT0_ADDRESS + 0x1000000;
68 init.tasks[4].size = INIT0_SIZE;
[7224093]69 init.tasks[5].addr = INIT0_ADDRESS + 0x1400000;
70 init.tasks[5].size = INIT0_SIZE;
[3247f0a]71 init.tasks[6].addr = INIT0_ADDRESS + 0x1800000;
72 init.tasks[6].size = INIT0_SIZE;
73 init.tasks[7].addr = INIT0_ADDRESS + 0x1c00000;
74 init.tasks[7].size = INIT0_SIZE;
[6ecc8bce]75}
76
[244f284]77void arch_pre_mm_init(void)
78{
[e2ec980f]79 /* Set Interruption Vector Address (i.e. location of interruption vector table). */
[7f1c620]80 iva_write((uintptr_t) &ivt);
[e2ec980f]81 srlz_d();
82
[2b50d7c]83 ski_init_console();
[6ecc8bce]84 it_init();
[244f284]85}
86
87void arch_post_mm_init(void)
88{
[d0c5901]89 ski_set_console_sysinfo();
[244f284]90}
[7453929]91
92void arch_pre_smp_init(void)
93{
94}
95
96void arch_post_smp_init(void)
97{
98}
[b994a60]99
100/** Enter userspace and never return. */
[0f250f9]101void userspace(uspace_arg_t *kernel_uarg)
[b994a60]102{
103 psr_t psr;
104 rsc_t rsc;
105
106 psr.value = psr_read();
107 psr.cpl = PL_USER;
108 psr.i = true; /* start with interrupts enabled */
109 psr.ic = true;
110 psr.ri = 0; /* start with instruction #0 */
[1065603e]111 psr.bn = 1; /* start in bank 0 */
[b994a60]112
113 __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
114 rsc.loadrs = 0;
115 rsc.be = false;
116 rsc.pl = PL_USER;
117 rsc.mode = 3; /* eager mode */
118
[7f1c620]119 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
120 ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
121 ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE,
122 (uintptr_t) kernel_uarg->uspace_uarg,
[0f250f9]123 psr.value, rsc.value);
[b994a60]124
125 while (1) {
126 ;
127 }
128}
[e1be3b6]129
130/** Set thread-local-storage pointer.
131 *
132 * We use r13 (a.k.a. tp) for this purpose.
133 */
[7f1c620]134unative_t sys_tls_set(unative_t addr)
[e1be3b6]135{
136 return 0;
137}
[41d33ac]138
139/** Acquire console back for kernel
140 *
141 */
142void arch_grab_console(void)
143{
[586262f]144 kbd_release=kbd_uspace;
145 kbd_uspace=0;
[41d33ac]146}
147/** Return console to userspace
148 *
149 */
150void arch_release_console(void)
151{
[586262f]152 kbd_uspace=kbd_release;
[41d33ac]153}
[b45c443]154
[06e1e95]155/** @}
[b45c443]156 */
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