source: mainline/kernel/arch/ia64/src/ia64.c@ 972c60ce

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 972c60ce was d75628da, checked in by Jakub Jermar <jakub@…>, 14 years ago

Set Interruption Vector Address register before any kernel C code can
generate a speculation exception.

  • Property mode set to 100644
File size: 7.7 KB
RevLine 
[2a0047fc]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
[2a0047fc]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[244f284]35#include <arch.h>
[c2417bc]36#include <arch/drivers/ski.h>
[154049e]37#include <arch/drivers/it.h>
[e2ec980f]38#include <arch/interrupt.h>
39#include <arch/barrier.h>
[b994a60]40#include <arch/asm.h>
41#include <arch/register.h>
[d99c1d2]42#include <typedefs.h>
[b994a60]43#include <arch/context.h>
[5c089c3a]44#include <arch/stack.h>
[b994a60]45#include <arch/mm/page.h>
[3a2f8aa]46#include <interrupt.h>
[b994a60]47#include <mm/as.h>
48#include <config.h>
[4872160]49#include <macros.h>
[b994a60]50#include <userspace.h>
[a8c48241]51#include <console/console.h>
[c0699467]52#include <abi/proc/uarg.h>
[e1be3b6]53#include <syscall/syscall.h>
[de57e060]54#include <ddi/irq.h>
[743ffa6e]55#include <arch/bootinfo.h>
[91825d90]56#include <genarch/drivers/legacy/ia32/io.h>
[f245145]57#include <genarch/drivers/ega/ega.h>
[411b6a6]58#include <genarch/kbrd/kbrd.h>
[4c84368e]59#include <genarch/srln/srln.h>
[411b6a6]60#include <genarch/drivers/i8042/i8042.h>
[4c84368e]61#include <genarch/drivers/ns16550/ns16550.h>
62#include <arch/drivers/kbd.h>
[59e4864]63#include <smp/smp.h>
64#include <smp/ipi.h>
65#include <arch/atomic.h>
66#include <panic.h>
67#include <print.h>
[46321fb]68#include <sysinfo/sysinfo.h>
[19f857a]69#include <str.h>
[59e4864]70
[666773c]71/* NS16550 as a COM 1 */
[449d4ecc]72#define NS16550_IRQ (4 + LEGACY_INTERRUPT_BASE)
[743ffa6e]73
74bootinfo_t *bootinfo;
[586262f]75
[666773c]76static uint64_t iosapic_base = 0xfec00000;
[323a5aaf]77
[06f96234]78/** Performs ia64-specific initialization before main_bsp() is called. */
[6ecc8bce]79void arch_pre_main(void)
80{
[4872160]81 init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
82 size_t i;
[6c441cf8]83 for (i = 0; i < init.cnt; i++) {
[666773c]84 init.tasks[i].addr =
85 ((unsigned long) bootinfo->taskmap.tasks[i].addr) |
86 VRN_MASK;
[6c441cf8]87 init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
[f4b1535]88 str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
89 bootinfo->taskmap.tasks[i].name);
[743ffa6e]90 }
[6ecc8bce]91}
92
[244f284]93void arch_pre_mm_init(void)
94{
95}
96
[323a5aaf]97static void iosapic_init(void)
98{
[96b02eb9]99 uint64_t IOSAPIC = PA2KA((sysarg_t)(iosapic_base)) | FW_OFFSET;
[323a5aaf]100 int i;
101
[2b70a6e]102 int myid, myeid;
[323a5aaf]103
[666773c]104 myid = ia64_get_cpu_id();
105 myeid = ia64_get_cpu_eid();
[50b3d30]106
[666773c]107 for (i = 0; i < 16; i++) {
108 if (i == 2)
109 continue; /* Disable Cascade interrupt */
110 ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i;
[323a5aaf]111 srlz_d();
[666773c]112 ((uint32_t *)(IOSAPIC + 0x10))[0] = LEGACY_INTERRUPT_BASE + i;
[323a5aaf]113 srlz_d();
[666773c]114 ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i + 1;
[323a5aaf]115 srlz_d();
[666773c]116 ((uint32_t *)(IOSAPIC + 0x10))[0] = myid << (56 - 32) |
117 myeid << (48 - 32);
[323a5aaf]118 srlz_d();
119 }
120
121}
122
[244f284]123void arch_post_mm_init(void)
124{
[666773c]125 if (config.cpu_active == 1) {
[323a5aaf]126 iosapic_init();
[59e4864]127 irq_init(INR_COUNT, INR_COUNT);
128 }
[2270bef]129 it_init();
[244f284]130}
[7453929]131
[26678e5]132void arch_post_cpu_init(void)
133{
134}
135
[7453929]136void arch_pre_smp_init(void)
137{
138}
139
140void arch_post_smp_init(void)
141{
[eff1f033]142 static const char *platform;
143
144 /* Set platform name. */
145#ifdef MACHINE_ski
[3714e79]146 platform = "ski";
[eff1f033]147#endif
148#ifdef MACHINE_i460GX
149 platform = "i460GX";
150#endif
151 sysinfo_set_item_data("platform", NULL, (void *) platform,
152 str_size(platform));
153
[c2417bc]154#ifdef MACHINE_ski
155 ski_instance_t *ski_instance = skiin_init();
156 if (ski_instance) {
157 srln_instance_t *srln_instance = srln_init();
158 if (srln_instance) {
159 indev_t *sink = stdin_wire();
160 indev_t *srln = srln_wire(srln_instance, sink);
161 skiin_wire(ski_instance, srln);
162 }
163 }
164
[a71c158]165 outdev_t *skidev = skiout_init();
166 if (skidev)
167 stdout_wire(skidev);
[1462d35]168#endif
169
[2270bef]170#ifdef CONFIG_EGA
[a71c158]171 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
172 if (egadev)
173 stdout_wire(egadev);
[2270bef]174#endif
[1462d35]175
[59e4864]176#ifdef CONFIG_NS16550
[c2417bc]177 ns16550_instance_t *ns16550_instance
[84afc7b]178 = ns16550_init((ns16550_t *) NS16550_BASE, NS16550_IRQ, NULL, NULL);
[c2417bc]179 if (ns16550_instance) {
180 srln_instance_t *srln_instance = srln_init();
181 if (srln_instance) {
182 indev_t *sink = stdin_wire();
183 indev_t *srln = srln_wire(srln_instance, sink);
184 ns16550_wire(ns16550_instance, srln);
185 }
186 }
[1462d35]187
[449d4ecc]188 sysinfo_set_item_val("kbd", NULL, true);
189 sysinfo_set_item_val("kbd.inr", NULL, NS16550_IRQ);
[4c7257b]190 sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
[ff685c9]191 sysinfo_set_item_val("kbd.address.physical", NULL,
192 (uintptr_t) NS16550_BASE);
193 sysinfo_set_item_val("kbd.address.kernel", NULL,
194 (uintptr_t) NS16550_BASE);
[449d4ecc]195#endif
196
197#ifdef CONFIG_I8042
[c2417bc]198 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
199 if (i8042_instance) {
200 kbrd_instance_t *kbrd_instance = kbrd_init();
201 if (kbrd_instance) {
202 indev_t *sink = stdin_wire();
203 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
204 i8042_wire(i8042_instance, kbrd);
205 }
206 }
[1462d35]207
[03a4476]208 sysinfo_set_item_val("i8042", NULL, true);
209 sysinfo_set_item_val("i8042.inr_a", NULL, IRQ_KBD);
210 sysinfo_set_item_val("i8042.inr_b", NULL, IRQ_MOUSE);
211 sysinfo_set_item_val("i8042.address.physical", NULL,
[ff685c9]212 (uintptr_t) I8042_BASE);
[03a4476]213 sysinfo_set_item_val("i8042.address.kernel", NULL,
[ff685c9]214 (uintptr_t) I8042_BASE);
[59e4864]215#endif
[a70bda4]216
[f902d36]217 sysinfo_set_item_val("netif.ne2000.inr", NULL, IRQ_NE2000);
[a70bda4]218
[46321fb]219 sysinfo_set_item_val("ia64_iospace", NULL, true);
220 sysinfo_set_item_val("ia64_iospace.address", NULL, true);
221 sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, IO_OFFSET);
[7453929]222}
[b994a60]223
[59e4864]224
[b994a60]225/** Enter userspace and never return. */
[0f250f9]226void userspace(uspace_arg_t *kernel_uarg)
[b994a60]227{
228 psr_t psr;
229 rsc_t rsc;
230
231 psr.value = psr_read();
232 psr.cpl = PL_USER;
[666773c]233 psr.i = true; /* start with interrupts enabled */
[b994a60]234 psr.ic = true;
[666773c]235 psr.ri = 0; /* start with instruction #0 */
236 psr.bn = 1; /* start in bank 0 */
[b994a60]237
[e7b7be3f]238 asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
[b994a60]239 rsc.loadrs = 0;
240 rsc.be = false;
241 rsc.pl = PL_USER;
[666773c]242 rsc.mode = 3; /* eager mode */
[b994a60]243
[2f23341]244 /*
245 * Switch to userspace.
246 *
247 * When calculating stack addresses, mind the stack split between the
248 * memory stack and the RSE stack. Each occuppies STACK_SIZE / 2 bytes.
249 */
[7f1c620]250 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
[2f23341]251 ((uintptr_t) kernel_uarg->uspace_stack) + STACK_SIZE / 2 -
[666773c]252 ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
[2f23341]253 ((uintptr_t) kernel_uarg->uspace_stack) + STACK_SIZE / 2,
[666773c]254 (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
[b994a60]255
[666773c]256 while (1)
[b994a60]257 ;
258}
[e1be3b6]259
260/** Set thread-local-storage pointer.
261 *
262 * We use r13 (a.k.a. tp) for this purpose.
263 */
[96b02eb9]264sysarg_t sys_tls_set(sysarg_t addr)
[e1be3b6]265{
[a71c158]266 return 0;
[41d33ac]267}
[b45c443]268
[f74bbaf]269void arch_reboot(void)
270{
[013c4d6]271 pio_write_8((ioport8_t *)0x64, 0xfe);
[666773c]272 while (1)
273 ;
[f74bbaf]274}
275
[6da1013f]276/** Construct function pointer
277 *
278 * @param fptr function pointer structure
279 * @param addr function address
280 * @param caller calling function address
281 *
282 * @return address of the function pointer
283 *
284 */
285void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
286{
[96b02eb9]287 fptr->fnc = (sysarg_t) addr;
288 fptr->gp = ((sysarg_t *) caller)[1];
[6da1013f]289
290 return (void *) fptr;
291}
292
[3a2f8aa]293void irq_initialize_arch(irq_t *irq)
294{
295 (void) irq;
296}
297
[06e1e95]298/** @}
[b45c443]299 */
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