source: mainline/kernel/arch/ia64/include/register.h@ e5c1186

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e5c1186 was d99c1d2, checked in by Martin Decky <martin@…>, 16 years ago

use [u]int{8|16|32|64}_t type definitions as detected by the autotool
replace direct usage of arch/types.h with typedefs.h
  • Property mode set to 100644
File size: 8.1 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ia64_REGISTER_H_
36#define KERN_ia64_REGISTER_H_
37
38#define DCR_PP_MASK (1 << 0)
39#define DCR_BE_MASK (1 << 1)
40#define DCR_LC_MASK (1 << 2)
41#define DCR_DM_MASK (1 << 8)
42#define DCR_DP_MASK (1 << 9)
43#define DCR_DK_MASK (1 << 10)
44#define DCR_DX_MASK (1 << 11)
45#define DCR_DR_MASK (1 << 12)
46#define DCR_DA_MASK (1 << 13)
47#define DCR_DD_MASK (1 << 14)
48
49#define CR_IVR_MASK 0x0f
50
51#define PSR_IC_MASK (1 << 13)
52#define PSR_I_MASK (1 << 14)
53#define PSR_PK_MASK (1 << 15)
54#define PSR_DT_MASK (1 << 17)
55#define PSR_DFL_MASK (1 << 18)
56#define PSR_DFH_MASK (1 << 19)
57#define PSR_RT_MASK (1 << 27)
58#define PSR_IT_MASK (1 << 36)
59
60#define PSR_CPL_SHIFT 32
61#define PSR_CPL_MASK_SHIFTED 3
62
63#define PFM_MASK (~0x3fffffffff)
64
65#define RSC_MODE_MASK 3
66#define RSC_PL_MASK 12
67
68/** Application registers. */
69#define AR_KR0 0
70#define AR_KR1 1
71#define AR_KR2 2
72#define AR_KR3 3
73#define AR_KR4 4
74#define AR_KR5 5
75#define AR_KR6 6
76#define AR_KR7 7
77/* ARs 8-15 are reserved */
78#define AR_RSC 16
79#define AR_BSP 17
80#define AR_BSPSTORE 18
81#define AR_RNAT 19
82/* AR 20 is reserved */
83#define AR_FCR 21
84/* ARs 22-23 are reserved */
85#define AR_EFLAG 24
86#define AR_CSD 25
87#define AR_SSD 26
88#define AR_CFLG 27
89#define AR_FSR 28
90#define AR_FIR 29
91#define AR_FDR 30
92/* AR 31 is reserved */
93#define AR_CCV 32
94/* ARs 33-35 are reserved */
95#define AR_UNAT 36
96/* ARs 37-39 are reserved */
97#define AR_FPSR 40
98/* ARs 41-43 are reserved */
99#define AR_ITC 44
100/* ARs 45-47 are reserved */
101/* ARs 48-63 are ignored */
102#define AR_PFS 64
103#define AR_LC 65
104#define AR_EC 66
105/* ARs 67-111 are reserved */
106/* ARs 112-127 are ignored */
107
108/** Control registers. */
109#define CR_DCR 0
110#define CR_ITM 1
111#define CR_IVA 2
112/* CR3-CR7 are reserved */
113#define CR_PTA 8
114/* CR9-CR15 are reserved */
115#define CR_IPSR 16
116#define CR_ISR 17
117/* CR18 is reserved */
118#define CR_IIP 19
119#define CR_IFA 20
120#define CR_ITIR 21
121#define CR_IIPA 22
122#define CR_IFS 23
123#define CR_IIM 24
124#define CR_IHA 25
125/* CR26-CR63 are reserved */
126#define CR_LID 64
127#define CR_IVR 65
128#define CR_TPR 66
129#define CR_EOI 67
130#define CR_IRR0 68
131#define CR_IRR1 69
132#define CR_IRR2 70
133#define CR_IRR3 71
134#define CR_ITV 72
135#define CR_PMV 73
136#define CR_CMCV 74
137/* CR75-CR79 are reserved */
138#define CR_LRR0 80
139#define CR_LRR1 81
140/* CR82-CR127 are reserved */
141
142#ifndef __ASM__
143
144#include <typedefs.h>
145
146/** Processor Status Register. */
147typedef union {
148 uint64_t value;
149 struct {
150 unsigned int : 1;
151 unsigned int be : 1; /**< Big-Endian data accesses. */
152 unsigned int up : 1; /**< User Performance monitor enable. */
153 unsigned int ac : 1; /**< Alignment Check. */
154 unsigned int mfl : 1; /**< Lower floating-point register written. */
155 unsigned int mfh : 1; /**< Upper floating-point register written. */
156 unsigned int : 7;
157 unsigned int ic : 1; /**< Interruption Collection. */
158 unsigned int i : 1; /**< Interrupt Bit. */
159 unsigned int pk : 1; /**< Protection Key enable. */
160 unsigned int : 1;
161 unsigned int dt : 1; /**< Data address Translation. */
162 unsigned int dfl : 1; /**< Disabled Floating-point Low register set. */
163 unsigned int dfh : 1; /**< Disabled Floating-point High register set. */
164 unsigned int sp : 1; /**< Secure Performance monitors. */
165 unsigned int pp : 1; /**< Privileged Performance monitor enable. */
166 unsigned int di : 1; /**< Disable Instruction set transition. */
167 unsigned int si : 1; /**< Secure Interval timer. */
168 unsigned int db : 1; /**< Debug Breakpoint fault. */
169 unsigned int lp : 1; /**< Lower Privilege transfer trap. */
170 unsigned int tb : 1; /**< Taken Branch trap. */
171 unsigned int rt : 1; /**< Register Stack Translation. */
172 unsigned int : 4;
173 unsigned int cpl : 2; /**< Current Privilege Level. */
174 unsigned int is : 1; /**< Instruction Set. */
175 unsigned int mc : 1; /**< Machine Check abort mask. */
176 unsigned int it : 1; /**< Instruction address Translation. */
177 unsigned int id : 1; /**< Instruction Debug fault disable. */
178 unsigned int da : 1; /**< Disable Data Access and Dirty-bit faults. */
179 unsigned int dd : 1; /**< Data Debug fault disable. */
180 unsigned int ss : 1; /**< Single Step enable. */
181 unsigned int ri : 2; /**< Restart Instruction. */
182 unsigned int ed : 1; /**< Exception Deferral. */
183 unsigned int bn : 1; /**< Register Bank. */
184 unsigned int ia : 1; /**< Disable Instruction Access-bit faults. */
185 } __attribute__ ((packed));
186} psr_t;
187
188/** Register Stack Configuration Register */
189typedef union {
190 uint64_t value;
191 struct {
192 unsigned int mode : 2;
193 unsigned int pl : 2; /**< Privilege Level. */
194 unsigned int be : 1; /**< Big-endian. */
195 unsigned int : 11;
196 unsigned int loadrs : 14;
197 } __attribute__ ((packed));
198} rsc_t;
199
200/** External Interrupt Vector Register */
201typedef union {
202 uint8_t vector;
203 uint64_t value;
204} cr_ivr_t;
205
206/** Task Priority Register */
207typedef union {
208 uint64_t value;
209 struct {
210 unsigned int : 4;
211 unsigned int mic: 4; /**< Mask Interrupt Class. */
212 unsigned int : 8;
213 unsigned int mmi: 1; /**< Mask Maskable Interrupts. */
214 } __attribute__ ((packed));
215} cr_tpr_t;
216
217/** Interval Timer Vector */
218typedef union {
219 uint64_t value;
220 struct {
221 unsigned int vector : 8;
222 unsigned int : 4;
223 unsigned int : 1;
224 unsigned int : 3;
225 unsigned int m : 1; /**< Mask. */
226 } __attribute__ ((packed));
227} cr_itv_t;
228
229/** Interruption Status Register */
230typedef union {
231 uint64_t value;
232 struct {
233 union {
234 /** General Exception code field structuring. */
235 uint16_t code;
236 struct {
237 unsigned int ge_na : 4;
238 unsigned int ge_code : 4;
239 } __attribute__ ((packed));
240 };
241 uint8_t vector;
242 unsigned int : 8;
243 unsigned int x : 1; /**< Execute exception. */
244 unsigned int w : 1; /**< Write exception. */
245 unsigned int r : 1; /**< Read exception. */
246 unsigned int na : 1; /**< Non-access exception. */
247 unsigned int sp : 1; /**< Speculative load exception. */
248 unsigned int rs : 1; /**< Register stack. */
249 unsigned int ir : 1; /**< Incomplete Register frame. */
250 unsigned int ni : 1; /**< Nested Interruption. */
251 unsigned int so : 1; /**< IA-32 Supervisor Override. */
252 unsigned int ei : 2; /**< Excepting Instruction. */
253 unsigned int ed : 1; /**< Exception Deferral. */
254 unsigned int : 20;
255 } __attribute__ ((packed));
256} cr_isr_t;
257
258/** CPUID Register 3 */
259typedef union {
260 uint64_t value;
261 struct {
262 uint8_t number;
263 uint8_t revision;
264 uint8_t model;
265 uint8_t family;
266 uint8_t archrev;
267 } __attribute__ ((packed));
268} cpuid3_t;
269
270#endif /* !__ASM__ */
271
272#endif
273
274/** @}
275 */
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