source: mainline/kernel/arch/ia64/include/register.h@ 087768f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 087768f was c0699467, checked in by Martin Decky <martin@…>, 14 years ago

do not provide general access to kernel headers from uspace, only allow specific headers to be accessed or shared
externalize headers which serve as kernel/uspace API/ABI into a special tree
  • Property mode set to 100644
File size: 8.1 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ia64_REGISTER_H_
36#define KERN_ia64_REGISTER_H_
37
38#define DCR_PP_MASK (1 << 0)
39#define DCR_BE_MASK (1 << 1)
40#define DCR_LC_MASK (1 << 2)
41#define DCR_DM_MASK (1 << 8)
42#define DCR_DP_MASK (1 << 9)
43#define DCR_DK_MASK (1 << 10)
44#define DCR_DX_MASK (1 << 11)
45#define DCR_DR_MASK (1 << 12)
46#define DCR_DA_MASK (1 << 13)
47#define DCR_DD_MASK (1 << 14)
48
49#define CR_IVR_MASK 0x0f
50
51#define PSR_IC_MASK (1 << 13)
52#define PSR_I_MASK (1 << 14)
53#define PSR_PK_MASK (1 << 15)
54#define PSR_DT_MASK (1 << 17)
55#define PSR_DFL_MASK (1 << 18)
56#define PSR_DFH_MASK (1 << 19)
57#define PSR_RT_MASK (1 << 27)
58#define PSR_IT_MASK (1 << 36)
59
60#define PSR_CPL_SHIFT 32
61#define PSR_CPL_MASK_SHIFTED 3
62
63#define PSR_RI_SHIFT 41
64#define PSR_RI_LEN 2
65
66#define PFM_MASK (~0x3fffffffff)
67
68#define RSC_MODE_MASK 3
69#define RSC_PL_MASK 12
70
71/** Application registers. */
72#define AR_KR0 0
73#define AR_KR1 1
74#define AR_KR2 2
75#define AR_KR3 3
76#define AR_KR4 4
77#define AR_KR5 5
78#define AR_KR6 6
79#define AR_KR7 7
80/* ARs 8-15 are reserved */
81#define AR_RSC 16
82#define AR_BSP 17
83#define AR_BSPSTORE 18
84#define AR_RNAT 19
85/* AR 20 is reserved */
86#define AR_FCR 21
87/* ARs 22-23 are reserved */
88#define AR_EFLAG 24
89#define AR_CSD 25
90#define AR_SSD 26
91#define AR_CFLG 27
92#define AR_FSR 28
93#define AR_FIR 29
94#define AR_FDR 30
95/* AR 31 is reserved */
96#define AR_CCV 32
97/* ARs 33-35 are reserved */
98#define AR_UNAT 36
99/* ARs 37-39 are reserved */
100#define AR_FPSR 40
101/* ARs 41-43 are reserved */
102#define AR_ITC 44
103/* ARs 45-47 are reserved */
104/* ARs 48-63 are ignored */
105#define AR_PFS 64
106#define AR_LC 65
107#define AR_EC 66
108/* ARs 67-111 are reserved */
109/* ARs 112-127 are ignored */
110
111/** Control registers. */
112#define CR_DCR 0
113#define CR_ITM 1
114#define CR_IVA 2
115/* CR3-CR7 are reserved */
116#define CR_PTA 8
117/* CR9-CR15 are reserved */
118#define CR_IPSR 16
119#define CR_ISR 17
120/* CR18 is reserved */
121#define CR_IIP 19
122#define CR_IFA 20
123#define CR_ITIR 21
124#define CR_IIPA 22
125#define CR_IFS 23
126#define CR_IIM 24
127#define CR_IHA 25
128/* CR26-CR63 are reserved */
129#define CR_LID 64
130#define CR_IVR 65
131#define CR_TPR 66
132#define CR_EOI 67
133#define CR_IRR0 68
134#define CR_IRR1 69
135#define CR_IRR2 70
136#define CR_IRR3 71
137#define CR_ITV 72
138#define CR_PMV 73
139#define CR_CMCV 74
140/* CR75-CR79 are reserved */
141#define CR_LRR0 80
142#define CR_LRR1 81
143/* CR82-CR127 are reserved */
144
145#ifndef __ASM__
146
147/** Processor Status Register. */
148typedef union {
149 uint64_t value;
150 struct {
151 unsigned int : 1;
152 unsigned int be : 1; /**< Big-Endian data accesses. */
153 unsigned int up : 1; /**< User Performance monitor enable. */
154 unsigned int ac : 1; /**< Alignment Check. */
155 unsigned int mfl : 1; /**< Lower floating-point register written. */
156 unsigned int mfh : 1; /**< Upper floating-point register written. */
157 unsigned int : 7;
158 unsigned int ic : 1; /**< Interruption Collection. */
159 unsigned int i : 1; /**< Interrupt Bit. */
160 unsigned int pk : 1; /**< Protection Key enable. */
161 unsigned int : 1;
162 unsigned int dt : 1; /**< Data address Translation. */
163 unsigned int dfl : 1; /**< Disabled Floating-point Low register set. */
164 unsigned int dfh : 1; /**< Disabled Floating-point High register set. */
165 unsigned int sp : 1; /**< Secure Performance monitors. */
166 unsigned int pp : 1; /**< Privileged Performance monitor enable. */
167 unsigned int di : 1; /**< Disable Instruction set transition. */
168 unsigned int si : 1; /**< Secure Interval timer. */
169 unsigned int db : 1; /**< Debug Breakpoint fault. */
170 unsigned int lp : 1; /**< Lower Privilege transfer trap. */
171 unsigned int tb : 1; /**< Taken Branch trap. */
172 unsigned int rt : 1; /**< Register Stack Translation. */
173 unsigned int : 4;
174 unsigned int cpl : 2; /**< Current Privilege Level. */
175 unsigned int is : 1; /**< Instruction Set. */
176 unsigned int mc : 1; /**< Machine Check abort mask. */
177 unsigned int it : 1; /**< Instruction address Translation. */
178 unsigned int id : 1; /**< Instruction Debug fault disable. */
179 unsigned int da : 1; /**< Disable Data Access and Dirty-bit faults. */
180 unsigned int dd : 1; /**< Data Debug fault disable. */
181 unsigned int ss : 1; /**< Single Step enable. */
182 unsigned int ri : 2; /**< Restart Instruction. */
183 unsigned int ed : 1; /**< Exception Deferral. */
184 unsigned int bn : 1; /**< Register Bank. */
185 unsigned int ia : 1; /**< Disable Instruction Access-bit faults. */
186 } __attribute__ ((packed));
187} psr_t;
188
189/** Register Stack Configuration Register */
190typedef union {
191 uint64_t value;
192 struct {
193 unsigned int mode : 2;
194 unsigned int pl : 2; /**< Privilege Level. */
195 unsigned int be : 1; /**< Big-endian. */
196 unsigned int : 11;
197 unsigned int loadrs : 14;
198 } __attribute__ ((packed));
199} rsc_t;
200
201/** External Interrupt Vector Register */
202typedef union {
203 uint8_t vector;
204 uint64_t value;
205} cr_ivr_t;
206
207/** Task Priority Register */
208typedef union {
209 uint64_t value;
210 struct {
211 unsigned int : 4;
212 unsigned int mic: 4; /**< Mask Interrupt Class. */
213 unsigned int : 8;
214 unsigned int mmi: 1; /**< Mask Maskable Interrupts. */
215 } __attribute__ ((packed));
216} cr_tpr_t;
217
218/** Interval Timer Vector */
219typedef union {
220 uint64_t value;
221 struct {
222 unsigned int vector : 8;
223 unsigned int : 4;
224 unsigned int : 1;
225 unsigned int : 3;
226 unsigned int m : 1; /**< Mask. */
227 } __attribute__ ((packed));
228} cr_itv_t;
229
230/** Interruption Status Register */
231typedef union {
232 uint64_t value;
233 struct {
234 union {
235 /** General Exception code field structuring. */
236 uint16_t code;
237 struct {
238 unsigned int ge_na : 4;
239 unsigned int ge_code : 4;
240 } __attribute__ ((packed));
241 };
242 uint8_t vector;
243 unsigned int : 8;
244 unsigned int x : 1; /**< Execute exception. */
245 unsigned int w : 1; /**< Write exception. */
246 unsigned int r : 1; /**< Read exception. */
247 unsigned int na : 1; /**< Non-access exception. */
248 unsigned int sp : 1; /**< Speculative load exception. */
249 unsigned int rs : 1; /**< Register stack. */
250 unsigned int ir : 1; /**< Incomplete Register frame. */
251 unsigned int ni : 1; /**< Nested Interruption. */
252 unsigned int so : 1; /**< IA-32 Supervisor Override. */
253 unsigned int ei : 2; /**< Excepting Instruction. */
254 unsigned int ed : 1; /**< Exception Deferral. */
255 unsigned int : 20;
256 } __attribute__ ((packed));
257} cr_isr_t;
258
259/** CPUID Register 3 */
260typedef union {
261 uint64_t value;
262 struct {
263 uint8_t number;
264 uint8_t revision;
265 uint8_t model;
266 uint8_t family;
267 uint8_t archrev;
268 } __attribute__ ((packed));
269} cpuid3_t;
270
271#endif /* !__ASM__ */
272
273#endif
274
275/** @}
276 */
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