source: mainline/kernel/arch/ia64/include/mm/page.h@ 59e4864

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 59e4864 was 59e4864, checked in by Jakub Vana <jakub.vana@…>, 17 years ago

Alfa of SMP support on IA64
  • Property mode set to 100644
File size: 6.7 KB
Line 
1/*
2 * Copyright (c) 2005 - 2006 Jakub Jermar
3 * Copyright (c) 2006 Jakub Vana
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup ia64mm
31 * @{
32 */
33/** @file
34 */
35
36#ifndef KERN_ia64_PAGE_H_
37#define KERN_ia64_PAGE_H_
38
39#include <arch/mm/frame.h>
40
41#define PAGE_SIZE FRAME_SIZE
42#define PAGE_WIDTH FRAME_WIDTH
43
44#ifdef KERNEL
45
46/** Bit width of the TLB-locked portion of kernel address space. */
47#define KERNEL_PAGE_WIDTH 28 /* 256M */
48#define IO_PAGE_WIDTH 26 /* 64M */
49#define FW_PAGE_WIDTH 28 /* 256M */
50
51/** Staticly mapped IO spaces */
52
53/* Firmware area (bellow 4GB in phys mem) */
54#define FW_OFFSET 0x00000000F0000000
55/* Legacy IO space */
56#define IO_OFFSET 0x0001000000000000
57/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/
58#define VIO_OFFSET 0x0002000000000000
59
60
61
62
63#define PPN_SHIFT 12
64
65#define VRN_SHIFT 61
66#define VRN_MASK (7LL << VRN_SHIFT)
67#define VA2VRN(va) ((va)>>VRN_SHIFT)
68
69#ifdef __ASM__
70#define VRN_KERNEL 7
71#else
72#define VRN_KERNEL 7LL
73#endif
74
75#define REGION_REGISTERS 8
76
77#define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
78#define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
79
80#define VHPT_WIDTH 20 /* 1M */
81#define VHPT_SIZE (1 << VHPT_WIDTH)
82
83#define PTA_BASE_SHIFT 15
84
85/** Memory Attributes. */
86#define MA_WRITEBACK 0x0
87#define MA_UNCACHEABLE 0x4
88
89/** Privilege Levels. Only the most and the least privileged ones are ever used. */
90#define PL_KERNEL 0x0
91#define PL_USER 0x3
92
93/* Access Rigths. Only certain combinations are used by the kernel. */
94#define AR_READ 0x0
95#define AR_EXECUTE 0x1
96#define AR_WRITE 0x2
97
98#ifndef __ASM__
99
100#include <arch/mm/as.h>
101#include <arch/mm/frame.h>
102#include <arch/interrupt.h>
103#include <arch/barrier.h>
104#include <arch/mm/asid.h>
105#include <arch/types.h>
106#include <debug.h>
107
108struct vhpt_tag_info {
109 unsigned long long tag : 63;
110 unsigned ti : 1;
111} __attribute__ ((packed));
112
113union vhpt_tag {
114 struct vhpt_tag_info tag_info;
115 unsigned tag_word;
116};
117
118struct vhpt_entry_present {
119 /* Word 0 */
120 unsigned p : 1;
121 unsigned : 1;
122 unsigned ma : 3;
123 unsigned a : 1;
124 unsigned d : 1;
125 unsigned pl : 2;
126 unsigned ar : 3;
127 unsigned long long ppn : 38;
128 unsigned : 2;
129 unsigned ed : 1;
130 unsigned ig1 : 11;
131
132 /* Word 1 */
133 unsigned : 2;
134 unsigned ps : 6;
135 unsigned key : 24;
136 unsigned : 32;
137
138 /* Word 2 */
139 union vhpt_tag tag;
140
141 /* Word 3 */
142 uint64_t ig3 : 64;
143} __attribute__ ((packed));
144
145struct vhpt_entry_not_present {
146 /* Word 0 */
147 unsigned p : 1;
148 unsigned long long ig0 : 52;
149 unsigned ig1 : 11;
150
151 /* Word 1 */
152 unsigned : 2;
153 unsigned ps : 6;
154 unsigned long long ig2 : 56;
155
156 /* Word 2 */
157 union vhpt_tag tag;
158
159 /* Word 3 */
160 uint64_t ig3 : 64;
161} __attribute__ ((packed));
162
163typedef union vhpt_entry {
164 struct vhpt_entry_present present;
165 struct vhpt_entry_not_present not_present;
166 uint64_t word[4];
167} vhpt_entry_t;
168
169struct region_register_map {
170 unsigned ve : 1;
171 unsigned : 1;
172 unsigned ps : 6;
173 unsigned rid : 24;
174 unsigned : 32;
175} __attribute__ ((packed));
176
177typedef union region_register {
178 struct region_register_map map;
179 unsigned long long word;
180} region_register;
181
182struct pta_register_map {
183 unsigned ve : 1;
184 unsigned : 1;
185 unsigned size : 6;
186 unsigned vf : 1;
187 unsigned : 6;
188 unsigned long long base : 49;
189} __attribute__ ((packed));
190
191typedef union pta_register {
192 struct pta_register_map map;
193 uint64_t word;
194} pta_register;
195
196/** Return Translation Hashed Entry Address.
197 *
198 * VRN bits are used to read RID (ASID) from one
199 * of the eight region registers registers.
200 *
201 * @param va Virtual address including VRN bits.
202 *
203 * @return Address of the head of VHPT collision chain.
204 */
205static inline uint64_t thash(uint64_t va)
206{
207 uint64_t ret;
208
209 asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
210
211 return ret;
212}
213
214/** Return Translation Hashed Entry Tag.
215 *
216 * VRN bits are used to read RID (ASID) from one
217 * of the eight region registers.
218 *
219 * @param va Virtual address including VRN bits.
220 *
221 * @return The unique tag for VPN and RID in the collision chain returned by thash().
222 */
223static inline uint64_t ttag(uint64_t va)
224{
225 uint64_t ret;
226
227 asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
228
229 return ret;
230}
231
232/** Read Region Register.
233 *
234 * @param i Region register index.
235 *
236 * @return Current contents of rr[i].
237 */
238static inline uint64_t rr_read(index_t i)
239{
240 uint64_t ret;
241 ASSERT(i < REGION_REGISTERS);
242 asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
243 return ret;
244}
245
246/** Write Region Register.
247 *
248 * @param i Region register index.
249 * @param v Value to be written to rr[i].
250 */
251static inline void rr_write(index_t i, uint64_t v)
252{
253 ASSERT(i < REGION_REGISTERS);
254 asm volatile (
255 "mov rr[%0] = %1\n"
256 :
257 : "r" (i << VRN_SHIFT), "r" (v)
258 );
259}
260
261/** Read Page Table Register.
262 *
263 * @return Current value stored in PTA.
264 */
265static inline uint64_t pta_read(void)
266{
267 uint64_t ret;
268
269 asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
270
271 return ret;
272}
273
274/** Write Page Table Register.
275 *
276 * @param v New value to be stored in PTA.
277 */
278static inline void pta_write(uint64_t v)
279{
280 asm volatile ("mov cr.pta = %0\n" : : "r" (v));
281}
282
283extern void page_arch_init(void);
284
285extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
286extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
287extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
288
289#endif /* __ASM__ */
290
291#endif /* KERNEL */
292
293#endif
294
295/** @}
296 */
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