source: mainline/kernel/arch/ia64/include/interrupt.h@ 6da1013f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6da1013f was 6da1013f, checked in by Martin Decky <martin@…>, 16 years ago

simplify configuration
introduce arch_construct_function and inb/outb (sometimes empty) on all platforms
various code cleanup
  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64interrupt
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ia64_INTERRUPT_H_
36#define KERN_ia64_INTERRUPT_H_
37
38#include <arch/types.h>
39#include <arch/register.h>
40
41/** ia64 has 256 INRs. */
42#define INR_COUNT 256
43
44/*
45 * We need to keep this just to compile.
46 * We might eventually move interrupt/ stuff
47 * to genarch.
48 */
49#define IVT_ITEMS 0
50#define IVT_FIRST 0
51
52/** External Interrupt vectors. */
53
54#define VECTOR_TLB_SHOOTDOWN_IPI 0xf0
55#define INTERRUPT_TIMER 255
56#define IRQ_KBD (0x01 + LEGACY_INTERRUPT_BASE)
57#define IRQ_MOUSE (0x0c + LEGACY_INTERRUPT_BASE)
58#define INTERRUPT_SPURIOUS 15
59#define LEGACY_INTERRUPT_BASE 0x20
60
61/** General Exception codes. */
62#define GE_ILLEGALOP 0
63#define GE_PRIVOP 1
64#define GE_PRIVREG 2
65#define GE_RESREGFLD 3
66#define GE_DISBLDISTRAN 4
67#define GE_ILLEGALDEP 8
68
69#define EOI 0 /**< The actual value doesn't matter. */
70
71typedef struct {
72 uint128_t f2;
73 uint128_t f3;
74 uint128_t f4;
75 uint128_t f5;
76 uint128_t f6;
77 uint128_t f7;
78 uint128_t f8;
79 uint128_t f9;
80 uint128_t f10;
81 uint128_t f11;
82 uint128_t f12;
83 uint128_t f13;
84 uint128_t f14;
85 uint128_t f15;
86 uint128_t f16;
87 uint128_t f17;
88 uint128_t f18;
89 uint128_t f19;
90 uint128_t f20;
91 uint128_t f21;
92 uint128_t f22;
93 uint128_t f23;
94 uint128_t f24;
95 uint128_t f25;
96 uint128_t f26;
97 uint128_t f27;
98 uint128_t f28;
99 uint128_t f29;
100 uint128_t f30;
101 uint128_t f31;
102
103 uintptr_t ar_bsp;
104 uintptr_t ar_bspstore;
105 uintptr_t ar_bspstore_new;
106 uint64_t ar_rnat;
107 uint64_t ar_ifs;
108 uint64_t ar_pfs;
109 uint64_t ar_rsc;
110 uintptr_t cr_ifa;
111 cr_isr_t cr_isr;
112 uintptr_t cr_iipa;
113 psr_t cr_ipsr;
114 uintptr_t cr_iip;
115 uint64_t pr;
116 uintptr_t sp;
117
118 /*
119 * The following variables are defined only for break_instruction
120 * handler.
121 */
122 uint64_t in0;
123 uint64_t in1;
124 uint64_t in2;
125 uint64_t in3;
126 uint64_t in4;
127 uint64_t in5;
128 uint64_t in6;
129} istate_t;
130
131static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
132{
133 istate->cr_iip = retaddr;
134 istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */
135}
136
137static inline unative_t istate_get_pc(istate_t *istate)
138{
139 return istate->cr_iip;
140}
141
142static inline int istate_from_uspace(istate_t *istate)
143{
144 return (istate->cr_iip) < 0xe000000000000000ULL;
145}
146
147extern void *ivt;
148
149extern void general_exception(uint64_t vector, istate_t *istate);
150extern int break_instruction(uint64_t vector, istate_t *istate);
151extern void universal_handler(uint64_t vector, istate_t *istate);
152extern void nop_handler(uint64_t vector, istate_t *istate);
153extern void external_interrupt(uint64_t vector, istate_t *istate);
154extern void disabled_fp_register(uint64_t vector, istate_t *istate);
155
156extern void trap_virtual_enable_irqs(uint16_t irqmask);
157
158#endif
159
160/** @}
161 */
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